Datasheet

Peripheral Memory Mapped Registers

56F8365 Technical Data, Rev. 9

Freescale Semiconductor 59

DEC1_IMR $D Input Monitor Register

Table 4-19 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F1A0)

IPR 0 $0 Interrupt Priority Register 0

IPR 1 $1 Interrupt Priority Register 1

IPR 2 $2 Interrupt Priority Register 2

IPR 3 $3 Interrupt Priority Register 3

IPR 4 $4 Interrupt Priority Register 4

IPR 5 $5 Interrupt Priority Register 5

IPR 6 $6 Interrupt Priority Register 6

IPR 7 $7 Interrupt Priority Register 7

IPR 8 $8 Interrupt Priority Register 8

IPR 9 $9 Interrupt Priority Register 9

VBA $A Vector Base Address Register

FIM0 $B Fast Interrupt Match Register 0

FIVAL0 $C Fast Interrupt Vector Address Low 0 Register

FIVAH0 $D Fast Interrupt Vector Address High 0 Register

FIM1 $E Fast Interrupt Match Register 1

FIVAL1 $F Fast Interrupt Vector Address Low 1 Register

FIVAH1 $10 Fast Interrupt Vector Address High 1 Register

IRQP 0 $11 IRQ Pending Register 0

IRQP 1 $12 IRQ Pending Register 1

IRQP 2 $13 IRQ Pending Register 2

IRQP 3 $14 IRQ Pending Register 3

IRQP 4 $15 IRQ Pending Register 4

IRQP 5 $16 IRQ Pending Register 5

Reserved

ICTL $1D Interrupt Control Register

Reserved

Table 4-18 Quadrature Decoder 1 Registers Address Map (Continued)

(DEC1_BASE = $00 F190)

Quadrature Decoder 1 is NOT available in the 56F8165 device