Datasheet

Peripheral Memory Mapped Registers
56F8365 Technical Data, Rev. 9
Freescale Semiconductor 61
ADCA_HLMT 2 $1B High Limit Register 2
ADCA_HLMT 3 $1C High Limit Register 3
ADCA_HLMT 4 $1D High Limit Register 4
ADCA_HLMT 5 $1E High Limit Register 5
ADCA_HLMT 6 $1F High Limit Register 6
ADCA_HLMT 7 $20 High Limit Register 7
ADCA_OFS 0 $21 Offset Register 0
ADCA_OFS 1 $22 Offset Register 1
ADCA_OFS 2 $23 Offset Register 2
ADCA_OFS 3 $24 Offset Register 3
ADCA_OFS 4 $25 Offset Register 4
ADCA_OFS 5 $26 Offset Register 5
ADCA_OFS 6 $27 Offset Register 6
ADCA_OFS 7 $28 Offset Register 7
ADCA_POWER $29 Power Control Register
ADCA_CAL $2A ADC Calibration Register
Table 4-21 Analog-to-Digital Converter Registers Address Map
(ADCB_BASE = $00 F240)
Register Acronym Address Offset Register Description
ADCB_CR1 $0 Control Register 1
ADCB_CR2 $1 Control Register 2
ADCB_ZCC $2 Zero Crossing Control Register
ADCB_LST 1 $3 Channel List Register 1
ADCB_LST 2 $4 Channel List Register 2
ADCB_SDIS $5 Sample Disable Register
ADCB_STAT $6 Status Register
ADCB_LSTAT $7 Limit Status Register
ADCB_ZCSTAT $8 Zero Crossing Status Register
ADCB_RSLT 0 $9 Result Register 0
ADCB_RSLT 1 $A Result Register 1
ADCB_RSLT 2 $B Result Register 2
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCA_BASE = $00 F200)
Register Acronym Address Offset Register Description