Datasheet

56F8365 Technical Data, Rev. 9
62 Freescale Semiconductor
ADCB_RSLT 3 $C Result Register 3
ADCB_RSLT 4 $D Result Register 4
ADCB_RSLT 5 $E Result Register 5
ADCB_RSLT 6 $F Result Register 6
ADCB_RSLT 7 $10 Result Register 7
ADCB_LLMT 0 $11 Low Limit Register 0
ADCB_LLMT 1 $12 Low Limit Register 1
ADCB_LLMT 2 $13 Low Limit Register 2
ADCB_LLMT 3 $14 Low Limit Register 3
ADCB_LLMT 4 $15 Low Limit Register 4
ADCB_LLMT 5 $16 Low Limit Register 5
ADCB_LLMT 6 $17 Low Limit Register 6
ADCB_LLMT 7 $18 Low Limit Register 7
ADCB_HLMT 0 $19 High Limit Register 0
ADCB_HLMT 1 $1A High Limit Register 1
ADCB_HLMT 2 $1B High Limit Register 2
ADCB_HLMT 3 $1C High Limit Register 3
ADCB_HLMT 4 $1D High Limit Register 4
ADCB_HLMT 5 $1E High Limit Register 5
ADCB_HLMT 6 $1F High Limit Register 6
ADCB_HLMT 7 $20 High Limit Register 7
ADCB_OFS 0 $21 Offset Register 0
ADCB_OFS 1 $22 Offset Register 1
ADCB_OFS 2 $23 Offset Register 2
ADCB_OFS 3 $24 Offset Register 3
ADCB_OFS 4 $25 Offset Register 4
ADCB_OFS 5 $26 Offset Register 5
ADCB_OFS 6 $27 Offset Register 6
ADCB_OFS 7 $28 Offset Register 7
ADCB_POWER $29 Power Control Register
ADCB_CAL $2A ADC Calibration Register
Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCB_BASE = $00 F240)
Register Acronym Address Offset Register Description