Datasheet

56F8365 Technical Data, Rev. 9

68 Freescale Semiconductor

SIM_LSH_ID $7 Least Significant Half JTAG ID

SIM_PUDR $8 Pull-up Disable Register

Reserved

SIM_CLKOSR $A Clock Out Select Register

SIM_GPS $B Quad Decoder 1 / Timer B / SPI 1 Select Register

SIM_PCE $C Peripheral Clock Enable Register

SIM_ISALH $D I/O Short Address Location High Register

SIM_ISALL $E I/O Short Address Location Low Register

SIM_PCE2 $F Peripheral Clock Enable Register 2

Table 4-36 Power Supervisor Registers Address Map

(LVI_BASE = $00 F360)

LVI_CONTROL $0 Control Register

LVI_STATUS $1 Status Register

Table 4-37 Flash Module Registers Address Map

(FM_BASE = $00 F400)

FMCLKD $0 Clock Divider Register

FMMCR $1 Module Control Register

Reserved

FMSECH $3 Security High Half Register

FMSECL $4 Security Low Half Register

Reserved

FMPROT $10 Protection Register (Banked)

FMPROTB $11 Protection Boot Register (Banked)

Reserved

FMUSTAT $13 User Status Register (Banked)

FMCMD $14 Command Register (Banked)

Table 4-35 System Integration Module Registers Address Map (Continued)

(SIM_BASE = $00 F350)