Datasheet

Block Diagram
56F8365 Technical Data, Rev. 9
Freescale Semiconductor 81
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number.
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
5.4 Block Diagram
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
Priority
Level
2 -> 4
Decode
INT1
Priority
Level
2 -> 4
Decode
INT82
Level 0
82 -> 7
Priority
Encoder
any0
Level 3
82 -> 7
Priority
Encoder
any3
INT
VAB
IPIC
CONTROL
7
7
PIC_EN
IACK
SR[9:8]