Datasheet

56F8365 Technical Data, Rev. 9

Freescale Semiconductor 93

5.6.6.4 SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—

Bits 9–8

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.6.5 Reserved—Bits 7–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.6.6 SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—

Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.6.7 SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)—

Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.6.8 SPI 0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)—

Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2