56F8366/56F8166 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8366 Rev. 7 11/2009 freescale.
Document Revision History Version History Description of Change Rev 0 Pre-release, Alpha customers only Rev 1.0 Initial Public Release Rev 2.0 Added output voltage maximum value and note to clarify in Table 10-1; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. Clarified value and unit measure for Maximum allowed PD in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4.
56F8366/56F8166 General Description Note: Features in italics are NOT available in the 56F8166 device.
Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8366/56F8166 Features . . . . . . . . . . . . . 5 Device Description . . . . . . . . . . . . . . . . . . . . 7 Award-Winning Development Environment . 9 Architecture Block Diagram . . . . . . . . . . . . 10 Product Documentation . . . . . . . . . . . . . . . 14 Data Sheet Conventions . . . . . . . . . . . . . . 14 Part 2: Signal/Connection Descriptions . . . 15 2.1. Introduction . . . . . .
6F8366/56F8166 Features Part 1 Overview 1.1 56F8366/56F8166 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
1.1.3 Memory Note: Features in italics are NOT available in the 56F8166 device.
Device Description • • Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) — In the 56F8366, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B — In the 56F8166, SPI1 can alternately be used only as GPIO • • • • • • • • 1.1.
1.2.1 56F8366 Features The 56F8366 hybrid controller includes 512KB of Program Flash and 32KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 32KB of Data RAM. It also supports program execution from external memory. A total of 32KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas.
Award-Winning Development Environment bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot Flash page erase size is 512 bytes and the Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F8166 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality.
1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8166 device and are shaded in the following figures. The 56F8366/56F8166 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories, the external memory interface and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function.
Architecture Block Diagram 5 JTAG / EOnCE Boot Flash pdb_m[15:0] pab[20:0] Program Flash cdbw[31:0] Program RAM 56800E 17 CHIP TAP Controller EMI 16 6 TAP Linking Module xab1[23:0] xab2[23:0] External JTAG Port Address Data Control Data RAM Data Flash cdbr_m[31:0] xdb2_m[15:0] IPBus Bridge To Flash Con trol Logic Flash Memory Module NOT available on the 56F8166 device. IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Memory (FM) Module.
To/From IPBus Bridge Interrupt Controller CLKGEN (OSC/PLL) Low Voltage Interrupt Timer A 4 POR & LVI System POR Quadrature Decoder 0 2 RESET SIM Timer D COP Reset Timer B 4 COP 2 FlexCAN Quadrature Decoder 1 2 FlexCAN2 SPI 1 12 PWMA GPIOA GPIOB 13 PWMB GPIOC GPIOD ch3i ch2i 1 Timer C GPIOE ch3o ch2o GPIOF 4 2 2 8 ADCB SPI0 SCI0 ADCA SCI1 TEMP_SENSE 8 1 IPBus NOT available on the 56F8166 device.
Architecture Block Diagram Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
1.5 Product Documentation The documents in Table 1-3 are required for a complete description and proper design with the 56F8366/56F8166 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com.
Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8366 and 56F8166 are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin.
Power VDD_IO Power VDDA_ADC Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS Other Supply Ports PLL and Clock External Address Bus or GPIO External Data Bus or GPIO VCAP1 - VCAP4 VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO A0 - A5 (GPIOA8 - 13) A6 - A7 (GPIOE2 - 3) A8 - A15 (GPIOA0 - 7) GPIOB0 (A16) D0 - D6 (GPIOF9 - 15) D7 - D15 (GPIOF0 - 8) 7 1 1 1 1 1 5 1 1 4 2 1 1 1 56F8366 1 1 1 1 1 1 1 1 6 1 1 2 8 1 7 9 6 3 3 6 3 4 RD External Bus Control or GPIO WR PS / CS0 (GPIOD8) DS /
Introduction VDD_IO Power VDDA_ADC Power VDDA_OSC_PLL Power VSS Ground VSSA_ADC Ground OCR_DIS VCAP1 - VCAP4 Other Supply Ports VPP1 & VPP2 PLL and Clock External Data Bus or GPIO 1 1 5 1 1 1 1 6 7 9 WR PS (CS0)(GPIOD8) DS (CS1)(GPIOD9) GPIOD0 - 1 (CS2 - 3) SCI 0 or GPIO TXD0 (GPIOE0) RXD0 (GPIOE1) 1 HOME0 (TA3, GPIOC7) 1 SCLK0 1 1 1 1 1 TXD1 (GPIOD6) RXD1 (GPIOD7) TCK JTAG/ EOnCE Port TMS MISO0 SPI0 or GPIO SS0 (GPIOE7) (SCLK1, GPIOC0) (MOSI1, GPIOC1) (MISO1, GPIOC2) SPI
2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Note: Signals in italics are NOT available in the 56F8166 device. If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other states show the reset condition of the alternate function, which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type VSSA_ADC 103 Supply OCR_DIS 79 Input State During Reset Signal Description ADC Analog Ground — This pin supplies an analog ground to the ADC modules. Input On-Chip Regulator Disable — Tie this pin to VSS to enable the on-chip regulator Tie this pin to VDD to disable the on-chip regulator This pin is intended to be a static DC signal from power-up to shut down.
Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type CLKO 3 Output State During Reset In reset, output is disabled Signal Description Clock Output — This pin outputs a buffered clock signal. Using the SIM CLKO Select Register (SIM_CLKOSR), this pin can be programmed as any of the following: disabled, CLK_MSTR (system clock), IPBus clock, oscillator output, prescaler clock and postscaler clock. Other signals are also available for test purposes. See Part 6.5.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type A6 17 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Address Bus — A6 - A7 specify two of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A6–A7 and EMI control signals are tri-stated when the external bus is inactive.
Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset GPIOB0 33 Schmitt Input/ Output Input, pull-up enabled (A16) Output Signal Description Port B GPIO — This GPIO pin can be programmed as an input or output pin. Address Bus — A16 specifies one of the address lines for external program or data memory accesses.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type D7 28 Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Data Bus — D7 - D14 specify part of the data for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), D7 - D14 are tri-stated when the external bus is inactive.
Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type RD 45 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Read Enable — RD is asserted during external memory read cycles. When RD is asserted low, pins D0 - D15 become inputs and an external device is enabled onto the data bus. When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn pins.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type DS 47 Output (CS1) State During Reset In reset, output is disabled, pull-up is enabled Signal Description Data Memory Select — This signal is actually CS1 in the EMI, which is programmed at reset for compatibility with the 56F80x DS signal. DS is asserted low for external data memory access.
Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset GPIOD1 49 Schmitt Input/ Output Input, pull-up enabled Output (CS3) Signal Description Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. Chip Select — CS3 may be programmed within the EMI module to act as a chip select for specific areas of the external memory map.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type TXD1 42 Output (GPIOD6) Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Transmit Data — SCI1 transmit data output Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 6 in the GPIOD_PUR register.
Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type TRST 120 Schmitt Input State During Reset Input, pulled high internally Signal Description Test Reset — As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type INDEX0 141 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index — Quadrature Decoder 0, INDEX input (TA2) Schmitt Input/ Output TA2 — Timer A, Channel 2 (GPOPC6) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is INDEX0.
Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type MOSI0 132 Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Input/ Output (GPIOE5) Signal Description SPI 0 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type PHASEA1 6 Schmitt Input State During Reset Input, pull-up enabled Signal Description Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1. (TB0) Schmitt Input/ Output TB0 — Timer B, Channel 0 (SCLK1) Schmitt Input/ Output SPI 1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input.
Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type INDEX1 8 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index1 — Quadrature Decoder 1, INDEX input (TB2) Schmitt Input/ Output TB2 — Timer B, Channel 2 (MISO1) Schmitt Input/ Output SPI 1 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Name Pin No. Type PWMA0 62 Output PWMA0 - 5 — These are six PWMA outputs. PWMA1 64 In reset, output is disabled PWMA2 65 PWMA3 67 PWMA4 68 PWMA5 70 ISA0 113 Schmitt Input Input, pull-up enabled ISA0 - 2 — These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA.
Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Name Pin No.
Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset TD0 116 Schmitt Input/ Output Input, pull-up enabled (GPIOE10) TD1 (GPIOE11) 117 Schmitt Input/ Output Signal Description TD0 - TD1 — Timer D, Channels 0 and 1 Port E GPIO — These GPIO pins can be individually programmed as input or output pins. At reset, these pins default to Timer functionality.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type EXTBOOT 112 Schmitt Input State During Reset Input, pull-up enabled Signal Description External Boot — This input is tied to VDD to force the device to boot from off-chip memory (assuming that the on-chip Flash memory is not in a secure state). Otherwise, it is tied to ground. For details, see Table 4-4.
Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the specific OCCS block diagram to reference in the OCCS chapter in the 56F8300 Peripheral User Manual.
External Clock Operation The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
3.2.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-4. The external clock source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high when using an external clock source as well. XTAL EXTAL External Clock VSS Note: When using an external clocking source with this configuration, the input “CLKMODE” should be high and the COHL bit in the OSCTL register should be set to 1. Figure 3-4 Connecting an External Clock Register 3.
Program Map Note: Data Flash and Program RAM are NOT available on the 56F8166 device. Table 4-1 Chip Memory Configurations On-Chip Memory 56F8366 56F8166 Use Restrictions Program Flash 512KB 512KB Data Flash 32KB — Erase / Program via Flash interface unit and word writes to CDBW.
Table 4-3 Changing OMR MA Value During Normal Operation OMR MA Chip Operating Mode 0 Use internal P-space memory map configuration 1 Use external P-space memory map configuration – If MB = 0 at reset, changing this bit has no effect. The device’s external memory interface (EMI) can operate much like the 56F80x family’s EMI, or it can be operated in a mode similar to that used on other products in the 56800E family.
Program Map Note: Program RAM is NOT available on the 56F8166 device.
4.3 Interrupt Vector Table Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority.
Interrupt Vector Table Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + PLL 21 0-2 P:$2A PLL FM 22 0-2 P:$2C FM Access Error Interrupt FM 23 0-2 P:$2E FM Command Complete FM 24 0-2 P:$30 FM Command, data and address Buffers Empty Peripheral Interrupt Function Reserved FLEXCAN 26 0-2 P:$34 FLEXCAN Bus Off FLEXCAN 27 0-2 P:$36 FLEXCAN Error FLEXCAN 28 0-2 P:$38 FLEXCAN Wake Up FLEXCAN 29 0-2 P:$3A FLEXCAN Mes
Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + TMRC 56 0-2 P:$70 Timer C, Channel 0 TMRC 57 0-2 P:$72 Timer C, Channel 1 TMRC 58 0-2 P:$74 Timer C, Channel 2 TMRC 59 0-2 P:$76 Timer C, Channel 3 TMRB 60 0-2 P:$78 Timer B, Channel 0 TMRB 61 0-2 P:$7A Timer B, Channel 1 TMRB 62 0-2 P:$7C Timer B, Channel 2 TMRB 63 0-2 P:$7E Timer B, Channel 3 TMRA 64 0-2 P:$80 Timer A, Channel 0 TMRA 65 0-2 P:$82 Tim
Data Map 4.4 Data Map Note: Data Flash is NOT available on the 56F8166 device.
Program Memory BOOT_FLASH_START + $3FFF BOOT_FLASH_START = $04_0000 PROG_FLASH_START + $03_FFFF Data Memory FM_BASE + $14 32KB Boot Configure Field FM_BASE + $00 Unbanked Registers FM_PROG_MEM_TOP = $01_FFFF DATA_FLASH_START + $3FFF 256KB Program 32KB DATA_FLASH_START + $0000 BLOCK 1 Odd (2 Bytes) $02_0003 BLOCK 1 Even (2 Bytes) $02_0002 BLOCK 1 Odd (2 Bytes) $02_0001 BLOCK 1 Even (2 Bytes) $02_0000 PROG_FLASH_START + $02_0000 PROG_FLASH_START + $01_FFFF Banked Registers Note: Data Flash is NOT av
EOnCE Memory Map 4.
4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only. Table 4-9 summarizes base addresses for the set of peripherals on the 56F8366 and 56F8166 devices. Peripherals are listed in order of the base address.
Peripheral Memory Mapped Registers Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number SIM SIM X:$00 F350 4-35 Power Supervisor LVI X:$00 F360 4-36 FM FM X:$00 F400 4-37 FlexCAN FC X:$00 F800 4-38 FlexCAN2 FC X:$00 FA00 4-39 Table 4-10 External Memory Integration Registers Address Map (EMI_BASE = $00 F020) Register Acronym CSBAR 0 Address Offset $0 Register Description Chip Select Base Address Register 0 Reset Value 0x
Table 4-10 External Memory Integration Registers Address Map (Continued) (EMI_BASE = $00 F020) Register Acronym Address Offset Register Description CSOR 1 $9 Chip Select Option Register 1 CSOR 2 $A Chip Select Option Register 2 CSOR 3 $B Chip Select Option Register 3 CSOR 4 $C Chip Select Option Register 4 CSOR 5 $D Chip Select Option Register 5 CSOR 6 $E Chip Select Option Register 6 CSOR 7 $F Chip Select Option Register 7 CSTC 0 $10 Chip Select Timing Control Register 0 CSTC 1
Peripheral Memory Mapped Registers Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_COMSCR $A Comparator Status and Control Register Reserve TMRA1_CMP1 $10 Compare Register 1 TMRA1_CMP2 $11 Compare Register 2 TMRA1_CAP $12 Capture Register TMRA1_LOAD $13 Load Register TMRA1_HOLD $14 Hold Register TMRA1_CNT
Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA3_CNTR $35 Counter Register TMRA3_CTRL $36 Control Register TMRA3_SCR $37 Status and Control Register TMRA3_CMPLD1 $38 Comparator Load Register 1 TMRA3_CMPLD2 $39 Comparator Load Register 2 TMRA3_COMSC $3A Comparator Status and Control Register Table 4-12 Quad Timer B Registers Address Map (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56
Peripheral Memory Mapped Registers Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8166 device Register Acronym Address Offset Register Description TMRB1_CMPLD2 $19 Comparator Load Register 2 TMRB1_COMSCR $1A Comparator Status and Control Register Reserved TMRB2_CMP1 $20 Compare Register 1 TMRB2_CMP2 $21 Compare Register 2 TMRB2_CAP $22 Capture Register TMRB2_LOAD $23 Load Register TMRB2_HOLD $24 Hold Register
Table 4-13 Quad Timer C Registers Address Map (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC0_CMP1 $0 Compare Register 1 TMRC0_CMP2 $1 Compare Register 2 TMRC0_CAP $2 Capture Register TMRC0_LOAD $3 Load Register TMRC0_HOLD $4 Hold Register TMRC0_CNTR $5 Counter Register TMRC0_CTRL $6 Control Register TMRC0_SCR $7 Status and Control Register TMRC0_CMPLD1 $8 Comparator Load Register 1 TMRC0_CMPLD2 $9 Comparator Load Register 2 TMRC0_COMSCR $A
Peripheral Memory Mapped Registers Table 4-13 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC2_SCR $27 Status and Control Register TMRC2_CMPLD1 $28 Comparator Load Register 1 TMRC2_CMPLD2 $29 Comparator Load Register 2 TMRC2_COMSCR $2A Comparator Status and Control Register Reserved TMRC3_CMP1 $30 Compare Register 1 TMRC3_CMP2 $31 Compare Register 2 TMRC3_CAP $32 Capture Register TMRC3_LOAD $33 Load Re
Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8166 device Register Acronym Address Offset Register Description Reserved TMRD1_CMP1 $10 Compare Register 1 TMRD1_CMP2 $11 Compare Register 2 TMRD1_CAP $12 Capture Register TMRD1_LOAD $13 Load Register TMRD1_HOLD $14 Hold Register TMRD1_CNTR $15 Counter Register TMRD1_CTRL $16 Control Register TMRD1_SCR $17 Status and Control Register TMRD1_CMPLD1 $18 Comparat
Peripheral Memory Mapped Registers Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8166 device Register Acronym Address Offset Register Description TMRD3_CTRL $36 Control Register TMRD3_SCR $37 Status and Control Register TMRD3_CMPLD1 $38 Comparator Load Register 1 TMRD3_CMPLD2 $39 Comparator Load Register 2 TMRD3_COMSCR $3A Comparator Status and Control Register Table 4-15 Pulse Width Modulator A Registers Address M
Table 4-16 Pulse Width Modulator B Registers Address Map (PWMB_BASE = $00 F160) Register Acronym Address Offset Register Description PWMB_PMCTL $0 Control Register PWMB_PMFCTL $1 Fault Control Register PWMB_PMFSA $2 Fault Status Acknowledge Register PWMB_PMOUT $3 Output Control Register PWMB_PMCNT $4 Counter Register PWMB_PWMCM $5 Counter Modulo Register PWMB_PWMVAL0 $6 Value Register 0 PWMB_PWMVAL1 $7 Value Register 1 PWMB_PWMVAL2 $8 Value Register 2 PWMB_PWMVAL3 $9 Value Re
Peripheral Memory Mapped Registers Table 4-17 Quadrature Decoder 0 Registers Address Map (Continued) (DEC0_BASE = $00 F180) Register Acronym Address Offset Register Description DEC0_UPOS $7 Upper Position Counter Register DEC0_LPOS $8 Lower Position Counter Register DEC0_UPOSH $9 Upper Position Hold Register DEC0_LPOSH $A Lower Position Hold Register DEC0_UIR $B Upper Initialization Register DEC0_LIR $C Lower Initialization Register DEC0_IMR $D Input Monitor Register Table 4-18 Quad
Table 4-19 Interrupt Control Registers Address Map (ITCN_BASE = $00 F1A0) Register Acronym Address Offset Register Description IPR 0 $0 Interrupt Priority Register 0 IPR 1 $1 Interrupt Priority Register 1 IPR 2 $2 Interrupt Priority Register 2 IPR 3 $3 Interrupt Priority Register 3 IPR 4 $4 Interrupt Priority Register 4 IPR 5 $5 Interrupt Priority Register 5 IPR 6 $6 Interrupt Priority Register 6 IPR 7 $7 Interrupt Priority Register 7 IPR 8 $8 Interrupt Priority Register 8 IPR
Peripheral Memory Mapped Registers Table 4-20 Analog-to-Digital Converter Registers Address Map (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_CR 1 $0 Control Register 1 ADCA_CR 2 $1 Control Register 2 ADCA_ZCC $2 Zero Crossing Control Register ADCA_LST 1 $3 Channel List Register 1 ADCA_LST 2 $4 Channel List Register 2 ADCA_SDIS $5 Sample Disable Register ADCA_STAT $6 Status Register ADCA_LSTAT $7 Limit Status Register ADCA_ZCSTAT $8 Zero Cross
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_HLMT 6 $1F High Limit Register 6 ADCA_HLMT 7 $20 High Limit Register 7 ADCA_OFS 0 $21 Offset Register 0 ADCA_OFS 1 $22 Offset Register 1 ADCA_OFS 2 $23 Offset Register 2 ADCA_OFS 3 $24 Offset Register 3 ADCA_OFS 4 $25 Offset Register 4 ADCA_OFS 5 $26 Offset Register 5 ADCA_OFS 6 $27 Offset Register 6 ADCA_OFS 7 $28 Offset Re
Peripheral Memory Mapped Registers Table 4-21 Analog-to-Digital Converter Registers Address Map (ADCB_BASE = $00 F240) (Continued) Register Acronym Address Offset Register Description ADCB_RSLT 7 $10 Result Register 7 ADCB_LLMT 0 $11 Low Limit Register 0 ADCB_LLMT 1 $12 Low Limit Register 1 ADCB_LLMT 2 $13 Low Limit Register 2 ADCB_LLMT 3 $14 Low Limit Register 3 ADCB_LLMT 4 $15 Low Limit Register 4 ADCB_LLMT 5 $16 Low Limit Register 5 ADCB_LLMT 6 $17 Low Limit Register 6 ADCB_LL
Table 4-22 Temperature Sensor Register Address Map (TSENSOR_BASE = $00 F270) Temperature Sensor is NOT available in the 56F8166 device Register Acronym TSENSOR_CNTL Address Offset $0 Register Description Control Register Table 4-23 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00 F280) Register Acronym Address Offset Register Description SCI0_SCIBR $0 Baud Rate Register SCI0_SCICR $1 Control Register Reserved SCI0_SCISR $3 Status Register SCI0_SCIDR $4 Data Register
Peripheral Memory Mapped Registers Table 4-26 Serial Peripheral Interface 1 Registers Address Map (SPI1_BASE = $00 F2B0) Register Acronym Address Offset Register Description SPI1_SPSCR $0 Status and Control Register SPI1_SPDSR $1 Data Size Register SPI1_SPDRR $2 Data Receive Register SPI1_SPDTR $3 Data Transmitter Register Table 4-27 Computer Operating Properly Registers Address Map (COP_BASE = $00 F2C0) Register Acronym Address Offset Register Description COPCTL $0 Control Register CO
Table 4-29 GPIOA Registers Address Map (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_PUR $0 Pull-up Enable Register 0 x 3FFF GPIOA_DR $1 Data Register 0 x 0000 GPIOA_DDR $2 Data Direction Register 0 x 0000 GPIOA_PER $3 Peripheral Enable Register 0 x 3FFF GPIOA_IAR $4 Interrupt Assert Register 0 x 0000 GPIOA_IENR $5 Interrupt Enable Register 0 x 0000 GPIOA_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOA_IPR $7 Interrupt Pe
Peripheral Memory Mapped Registers Table 4-31 GPIOC Registers Address Map (GPIOC_BASE = $00 F310) Register Acronym Address Offset Register Description Reset Value GPIOC_PUR $0 Pull-up Enable Register 0 x 07FF GPIOC_DR $1 Data Register 0 x 0000 GPIOC_DDR $2 Data Direction Register 0 x 0000 GPIOC_PER $3 Peripheral Enable Register 0 x 07FF GPIOC_IAR $4 Interrupt Assert Register 0 x 0000 GPIOC_IENR $5 Interrupt Enable Register 0 x 0000 GPIOC_IPOLR $6 Interrupt Polarity Register 0
Table 4-33 GPIOE Registers Address Map (GPIOE_BASE = $00 F330) Register Acronym Address Offset Register Description Reset Value GPIOE_PUR $0 Pull-up Enable Register 0 x 3FFF GPIOE_DR $1 Data Register 0 x 0000 GPIOE_DDR $2 Data Direction Register 0 x 0000 GPIOE_PER $3 Peripheral Enable Register 0 x 3FFF GPIOE_IAR $4 Interrupt Assert Register 0 x 0000 GPIOE_IENR $5 Interrupt Enable Register 0 x 0000 GPIOE_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOE_IPR $7 Interrupt Pe
Peripheral Memory Mapped Registers Table 4-35 System Integration Module Registers Address Map (SIM_BASE = $00 F350) Register Acronym Address Offset Register Description SIM_CONTROL $0 Control Register SIM_RSTSTS $1 Reset Status Register SIM_SCR0 $2 Software Control Register 0 SIM_SCR1 $3 Software Control Register 1 SIM_SCR2 $4 Software Control Register 2 SIM_SCR3 $5 Software Control Register 3 SIM_MSH_ID $6 Most Significant Half JTAG ID SIM_LSH_ID $7 Least Significant Half JTAG ID
Table 4-37 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FMCLKD $0 Clock Divider Register FMMCR $1 Module Control Register Reserved FMSECH $3 Security High Half Register FMSECL $4 Security Low Half Register Reserved Reserved FMPROT $10 Protection Register (Banked) FMPROTB $11 Protection Boot Register (Banked) Reserved FMUSTAT $13 User Status Register (Banked) FMCMD $14 Command Register (Banked) Reserved Reserved FMOPT
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8166 device Register Acronym FCMAXMB Address Offset $6 Register Description Maximum Message Buffer Configuration Register Reserved FCRXGMASK_H $8 Receive Global Mask High Register FCRXGMASK_L $9 Receive Global Mask Low Register FCRX14MASK_H $A Receive Buffer 14 Mask High Register FCRX14MASK_L $B Receive Buffer 14 Mask Low Register FCRX15MASK_H $C R
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8166 device Register Acronym Address Offset Register Description Reserved FCMB2_CONTROL $50 Message Buffer 2 Control / Status Register FCMB2_ID_HIGH $51 Message Buffer 2 ID High Register FCMB2_ID_LOW $52 Message Buffer 2 ID Low Register FCMB2_DATA $53 Message Buffer 2 Data Register FCMB2_DATA $54 Message Buffer 2 Data Register FCMB2_DATA $55 Message Buffer 2 Data Register FCMB2_D
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8166 device Register Acronym FCMB5_DATA Address Offset $6E Register Description Message Buffer 5 Data Register Reserved FCMB6_CONTROL $70 Message Buffer 6 Control / Status Register FCMB6_ID_HIGH $71 Message Buffer 6 ID High Register FCMB6_ID_LOW $72 Message Buffer 6 ID Low Register FCMB6_DATA $73 Message Buffer 6 Data Register FCMB6_DATA $74 Messag
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FCMB9_DATA $8D Message Buffer 9 Data Register FCMB9_DATA $8E Message Buffer 9 Data Register Reserved FCMB10_CONTROL $90 Message Buffer 10 Control / Status Register FCMB10_ID_HIGH $91 Message Buffer 10 ID High Register FCMB10_ID_LOW $92 Message Buffer 10 ID Low Register FCMB10_DATA $93 Message Buffer 10 Data Register
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FCMB13_DATA $AC Message Buffer 13 Data Register FCMB13_DATA $AD Message Buffer 13 Data Register FCMB13_DATA $AE Message Buffer 13 Data Register Reserved FCMB14_CONTROL $B0 Message Buffer 14 Control / Status Register FCMB14_ID_HIGH $B1 Message Buffer 14 ID High Register FCMB14_ID_LOW
Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FC2IMASK2 $7 Interrupt Masks 2 Register FC2RXGMASK_H $8 Receive Global Mask High Register FC2RXGMASK_L $9 Receive Global Mask Low Register FC2RX14MASK_H $A Receive Buffer 14 Mask High Register FC2RX14MASK_L $B Receive Buffer 14 Mask Low Register FC2RX15MASK_H $C Receive Buffer 15 Mask High Register FC2RX15MASK_L
Peripheral Memory Mapped Registers Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FC2MB2_CONTROL $50 Message Buffer 2 Control / Status Register FC2MB2_ID_HIGH $51 Message Buffer 2 ID High Register FC2MB2_ID_LOW $52 Message Buffer 2 ID Low Register FC2MB2_DATA $53 Message Buffer 2 Data Register FC2MB2_DATA $54 Message Buffer 2 Data Register FC2MB2_DATA $55 Mes
Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description Reserved FC2MB6_CONTROL $70 Message Buffer 6 Control / Status Register FC2MB6_ID_HIGH $71 Message Buffer 6 ID High Register FC2MB6_ID_LOW $72 Message Buffer 6 ID Low Register FC2MB6_DATA $73 Message Buffer 6 Data Register FC2MB6_DATA $74 Message Buffer 6 Data Register FC2MB6_DATA $75 Message Buffer 6 Data Register
Peripheral Memory Mapped Registers Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8166 device Register Acronym FC2MB9_DATA Address Offset $8E Register Description Message Buffer 9 Data Register Reserved FC2MB10_CONTROL $90 Message Buffer 10 Control / Status Register FC2MB10_ID_HIGH $91 Message Buffer 10 ID High Register FC2MB10_ID_LOW $92 Message Buffer 10 ID Low Register FC2MB10_DATA $93 Message Buffer 10 Data Register FC2MB10
Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FC2MB13_DATA $AC Message Buffer 13 Data Register FC2MB13_DATA $AD Message Buffer 13 Data Register FC2MB13_DATA $AE Message Buffer 13 Data Register Reserved FC2MB14_CONTROL $B0 Message Buffer 14 Control / Status Register FC2MB14_ID_HIGH $B1 Message Buffer 14 ID High Register FC2MB14_ID_LOW $B2 Message Buffer 14 ID
Introduction Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt. 5.
Table 5-2 Interrupt Priority Encoding IPIC_LEVEL[1:0]1 Current Interrupt Priority Level Required Nested Exception Priority 00 No Interrupt or SWILP Priorities 0, 1, 2, 3 01 Priority 0 Priorities 1, 2, 3 10 Priority 1 Priorities 2, 3 11 Priorities 2 or 3 Priority 3 1. See IPIC field definition in Part 5.6.30.2. 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does.
Block Diagram 5.4 Block Diagram Priority Level INT1 Level 0 82 -> 7 Priority Encoder 2 -> 4 Decode any0 7 INT VAB CONTROL IPIC any3 Level 3 Priority Level INT82 82 -> 7 Priority Encoder 7 IACK SR[9:8] PIC_EN 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default.
5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers. Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F1A0) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.
Register Descriptions Add.
5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 15 14 Read 0 0 0 0 13 BKPT_U0 IPL Write RESET 12 0 11 10 STPCNT IPL 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.1.
Register Descriptions 5.6.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.2.
5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.
Register Descriptions 5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.6 Reserved—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.3.
5.6.4.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.2 GPIOE Interrupt Priority Level (GPIOE IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
Register Descriptions 5.6.4.5 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.6 FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs.
5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.2 SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.7 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs.
5.6.6.2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.
Register Descriptions 5.6.6.7 SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.
5.6.7.2 Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.3 Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.7.7 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.
5.6.8.2 Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.3 Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.8.6 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.7 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs.
5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.3 Reserved—Bits 11–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.9.
Register Descriptions 5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs.
5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.10.7 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.
5.6.12 Fast Interrupt 0 Match Register (FIM0) Base + $B 15 14 13 12 11 10 9 8 7 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 3 2 1 0 0 0 FAST INTERRUPT 0 Write RESET 4 0 0 0 0 0 Figure 5-14 Fast Interrupt 0 Match Register (FIM0) 5.6.12.1 Reserved—Bits 15–7 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.12.
Register Descriptions 5.6.14.1 Reserved—Bits 15–5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 5.6.
5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1) Base + $10 15 14 13 12 11 10 9 8 7 6 5 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 2 1 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH Write RESET 3 0 0 0 0 0 Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1) 5.6.17.1 Reserved—Bits 15–5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.17.
Register Descriptions 5.6.19.1 IRQ Pending (PENDING)—Bits 32–17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.20 IRQ Pending 2 Register (IRQP2) Base + $13 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [48:33] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.
5.6.22 IRQ Pending 4 Register (IRQP4) Base + $15 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [80:65] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-24 IRQ Pending 4 Register (IRQP4) 5.6.22.1 IRQ Pending (PENDING)—Bits 80–65 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.
Register Descriptions 5.6.28 Reserved—Base + 1B 5.6.29 Reserved—Base + 1C 5.6.30 ITCN Control Register (ICTL) Base + $1D 15 Read INT 14 13 12 11 10 IPIC 9 8 7 6 VAB INT_DIS Write RESET 0 0 0 1 0 0 0 5 0 0 0 0 4 3 2 1 0 1 IRQB STATE IRQA STATE IRQB EDG IRQA EDG 1 1 1 0 0 Figure 5-26 ITCN Control Register (ICTL) 5.6.30.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core.
5.6.30.5 Reserved—Bit 4 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3 This read-only bit reflects the state of the external IRQB pin. 5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2 This read-only bit reflects the state of the external IRQA pin. 5.6.30.8 IRQB Edge Pin (IRQB Edg)—Bit 1 This bit controls whether the external IRQB interrupt is edge- or level-sensitive.
Register Descriptions 5.6.32.2 FlexCAN2 Message Buffer Interrupt Priority Level (FlexCAN2_MSGBUF IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.32.
5.7 Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 5.7.2 ITCN After Reset After reset, all of the ITCN registers are in their default states.
Features 6.2 Features The SIM has the following features: • • • Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory Power-saving clock gating for peripheral Three power modes (Run, Wait, Stop) to control power utilization — Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation — Stop mode entry can optionally disable PLL and Oscillator (low power vs.
• Stop Mode When in Stop mode, the 56800E core, memory, and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode. 6.
Register Descriptions 6.5 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F350) Address Offset Address Acronym Register Name Section Location Base + $0 SIM_CONTROL Control Register 6.5.1 Base + $1 SIM_RSTSTS Reset Status Register 6.5.2 Base + $2 SIM_SCR0 Software Control Register 0 6.5.3 Base + $3 SIM_SCR1 Software Control Register 1 6.5.3 Base + $4 SIM_SCR2 Software Control Register 2 6.5.3 Base + $5 SIM_SCR3 Software Control Register 3 6.5.
Add.
Register Descriptions 6.5.1.2 EMI_MODE (EMI_MODE)—Bit 6 This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset. In addition, this pin can be used as a general purpose input pin after reset.
6.5.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.2.2 Software Reset (SWR)—Bit 5 When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.
Register Descriptions 6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (RESET pin, software reset, and COP reset). 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01D6.
6.5.6.1 Reserved —Bit 15 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.2 PWMA1—Bit 14 This bit controls the pull-up resistors on the FAULTA3 pin. 6.5.6.3 CAN—Bit 13 This bit controls the pull-up resistors on the CAN_RX pin. 6.5.6.4 EMI_MODE—Bit 12 This bit controls the pull-up resistors on the EMI_MODE pin. 6.5.6.5 RESET—Bit 11 This bit controls the pull-up resistors on the RESET pin. 6.5.6.
Register Descriptions 6.5.6.14 Reserved—Bit 2–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.7 CLKO Select Register (SIM_CLKOSR) The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are for test purposes only, and are subject to significant unspecified latencies at high frequencies.
6.5.7.6 • • Clockout Disable (CLKDIS)—Bit 5 0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL 1 = CLKOUT is tri-stated 6.5.7.7 CLockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO pin.
Register Descriptions GPIOC_PER Register GPIO Controlled 0 I/O Pad Control 1 SIM_ GPS Register 0 Quad Timer Controlled 1 SPI Controlled Figure 6-10 Overall Control of GPIOC Pads Using SIM_GPS Control Table 6-2 Control of GPIOC Pads Using SIM_GPS Control 1 GPIOC_PER GPIOC_DTR SIM_GPS Quad Timer SCR Register OEN bits Control Registers GPIO Input 0 0 — — GPIO Output 0 1 — — Quad Timer Input / Quad Decoder Input 2 1 — 0 0 Quad Timer Output / Quad Decoder Input 3 1 — 0 1 SPI inp
Two Input/Output pins associated with GPIOD can function as GPIO, EMI (default peripheral) or CAN2 (NOT available in the 56F8166 device) signals. GPIO is the default and is enabled/disabled via the GPIOD_PER, as shown in Figure 6-11 and Table 6-3. When GPIOD[1:0] are programmed to operate as peripheral input/output, then the choice between EMI and CAN2 inputs/outputs is made here in the GPS.
Register Descriptions Base + $B 15 14 13 12 11 10 9 8 7 6 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 5 4 3 2 1 0 D1 D0 C3 C2 C1 C0 0 0 0 0 0 0 Figure 6-12 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.8.2 GPIOD1 (D1)—Bit 5 This bit selects the alternate function for GPIOD1. • • 0 = CS3 1 = CAN2_RX 6.5.8.
6.5.9 Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip.
Register Descriptions 6.5.9.6 Decoder 0 Enable (DEC0)—Bit 10 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.7 Quad Timer D Enable (TMRD)—Bit 9 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.15 Pulse Width Modulator B Enable (PWMB)—1 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
Register Descriptions With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents prior to returning from interrupt. Note: The default value of this register set points to the EOnCE registers. Note: The pipeline delay between setting this register set and using short I/O addressing with the new value is three cycles.
6.5.11.2 CAN2 Enable—Bit 0 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.6 Clock Generation Overview The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz.
Stop and Wait Mode Disable Function 6.8 Stop and Wait Mode Disable Function Permanent Disable D Q D-FLOP C Reprogrammable Disable 56800E D STOP_DIS Q D-FLOP Clock Select C Reset R Note: Wait disable circuit is similar Figure 6-17 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down.
Part 7 Security Features The 56F8366/56F8166 offer security features intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array. The Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array. However, part of the security must lie with the user’s code.
Flash Access Blocking Mechanisms 7.2.2 Disabling EOnCE Access On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability and access to the ID register.
Flash Memory SYS_CLK input 2 clock DIVIDER 7 FMCLKD 7 FM_CLKDIV JTAG 7 FM_ERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz.
Introduction 7.2.4 Product Analysis The recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows backdoor key access must be set.
Table 8-1 56F8366 GPIO Ports Configuration GPIO Port Port Width Available Pins in 56F8366 A 14 14 14 pins - EMI Address pins EMI Address B 8 1 1 pin - EMI Address pin 7 pins - EMI Address pins - Not available in this package EMI Address N/A C 11 11 4 pins -DEC1 / TMRB / SPI1 4 pins -DEC0 / TMRA 3 pins -PWMA current sense DEC1 / TMRB DEC0 / TMRA PWMA current sense D 13 9 2 pins - EMI CSn 4 pins - EMI CSn - Not available in this package 2 pins - SCI1 2 pins - EMI CSn 3 pins -PWMB current
Configuration Table 8-2 56F8166 GPIO Ports Configuration (Continued) GPIO Port Port Width Available Pins in 56F8166 E 14 11 2 pins - SCI0 2 pins - EMI Address pins 4 pins - SPI0 1 pin - TMRC 1 pin - TMRC - Not available in this package 2 pins - Dedicated GPIO 2 pins - TMRD - Not available in this package SCI0 EMI Address SPI0 TMRC N/A GPIO N/A F 16 16 16 pins - EMI Data EMI Data Peripheral Function Reset Function Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8366/56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIOB 1This GPIO Bit Reset Function Functional Signal Package PIn 0 GPIO1 A16 33 1 N/A 2 N/A 3 N/A 4 N/A 5 N/A 6 N/A 7 N/A is a function of the EMI_MODE, EXTBOOT, and Flash security settings at reset.
Configuration Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8366/56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIOD GPIOE GPIO Bit Reset Function Functional Signal Package PIn 0 GPIO CS2 / CAN2_TX 48 1 GPIO CS3 / CAN2_RX 49 2 N/A 3 N/A 4 N/A 5 N/A 6 Peripheral TXD1 42 7 Peripheral RXD1 43 8 Peripheral PS / CS0 46 9 Peripheral DS / CS1 47 10 Peripheral ISB0 50 11 Peripheral ISB1 52 12 P
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8366/56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIOF GPIO Bit Reset Function Functional Signal Package PIn 0 Peripheral D7 28 1 Peripheral D8 29 2 Peripheral D9 30 3 Peripheral D10 32 4 Peripheral D11 133 5 Peripheral D12 134 6 Peripheral D13 135 7 Peripheral D14 136 8 Peripheral D15 137 9 Peripheral D0 59 10 Peripheral D1 60 11 Periph
General Characteristics Part 10 Specifications 10.1 General Characteristics The 56F8366/56F8166 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.
Note: The 56F8166 device is guaranteed to 40MHz and specified to meet Industrial requirements only; CAN is NOT available on the 56F8166 device. Table 10-1 Absolute Maximum Ratings (VSS = VSSA_ADC = 0) Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Symbol Notes VDD_IO VDDA_ADC, VREFH VREFH must be less than or equal to VDDA_ADC VDDA_OSC_PLL Min Max Unit - 0.3 4.0 V - 0.3 4.0 V - 0.3 4.0 V VDD_CORE OCR_DIS is High - 0.3 3.
General Characteristics Table 10-2 56F8366/56F8166 ElectroStatic Discharge (ESD) Protection Characteristic Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 500 — — V Table 10-3 Thermal Characteristics6 Characteristic Comments Value Symbol Unit Notes 144-pin LQFP Junction to ambient Natural convection Junction to ambient (@1m/sec) RθJA 47.1 °C/W 2 RθJMA 43.
Note: The 56F8166 device is guaranteed to 40MHz and specified to meed Industrial requirements only; CAN is NOT available on the 56F8166 device. Table 10-4 Recommended Operating Conditions (VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL ) Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Symbol Notes VDD_IO VDDA_ADC, VREFH VREFH must be less than or Min Typ Max Unit 3 3.3 3.6 V 3 3.3 3.6 V 3 3.3 3.6 V 2.25 2.5 2.
DC Electrical Characteristics 10.2 DC Electrical Characteristics Note: The 56F8166 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8166 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Table 10-4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage VOH 2.4 — — V IOH = IOHmax Output Low Voltage VOL — — 0.
μA 0 –10 –30 –50 –70 –90 0 1 2 3 Volts Figure 10-1 Maximum Current — Schmitt Input DC Response –40 °C, 3.6 V Table 10-6 Power on Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1.75 1.8 1.9 V LVI, 2.5 volt Supply, trip point1 VEI2.5 — 2.14 — V LVI, 3.3 volt supply, trip point2 VEI3.3 — 2.7 — V Bias Current I bias — 110 130 μA 1. When VDD_CORE drops below VEI2.5, an interrupt is generated. 2. When VDD_CORE drops below VEI3.
DC Electrical Characteristics Table 10-7 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Enabled (OCR_DIS = Low) Mode IDD_IO1 IDD_ADC IDD_OSC_PLL 6mA 0μA 165μA Stop1 Test Conditions • 8MHz Device Clock • All peripheral clocks are off • ADC powered off • PLL powered off Stop2 5.1mA 0μA 155μA • External Clock is off • All peripheral clocks are off • ADC powered off • PLL powered off 1. No Output Switching 2.
Table 10-9. Regulator Parameters Characteristic Symbol Min Typical Max Unit Unloaded Output Voltage (0mA Load) VRNL 2.25 — 2.75 V Loaded Output Voltage (200mA load) VRL 2.25 — 2.75 V Line Regulation @ 250mA load (VDD33 ranges from 3.0V to 3.6V) VR 2.25 — 2.75 V Short Circuit Current ( output shorted to ground) Iss — — 700 mA I bias — 5.
AC Electrical Characteristics Table 10-11 Temperature Sense Parametrics Characteristics Symbol Min Typical Max Unit VTS0 — 1.370 — V VDDA_ADC 3.0 3.3 3.6 V Supply Current - OFF IDD-OFF — — 10 μA Supply Current - ON IDD-ON — — 250 μA Accuracy3,1 from -40°C to 150°C Using VTS = mT + VTS0 TACC -6.7 0 6.7 °C Resolution4, 5,1 RES — 0.104 — °C / bit Output Voltage @ VDDA_ADC = 3.3V, TJ =0°C1 Supply Voltage 1.
Data2 Valid Data1 Valid Data3 Valid Data2 Data1 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 10-3 Signal States 10.4 Flash Memory Characteristics Table 10-12 Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 Tprog 20 — — μs Erase time2 Terase 20 — — ms Tme 100 — — ms Mass erase time 1. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual for details.
Phase Locked Loop Timing VIH External Clock 90% 50% 10% 90% 50% 10% tfall tPW tPW trise VIL Note: The midpoint is VIL + (VIH – VIL)/2. Figure 10-4 External Clock Timing 10.6 Phase Locked Loop Timing Table 10-14 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 8.4 MHz PLL output frequency2 (fOUT) fop 160 — 260 MHz PLL stabilization time3 -40° to +125°C tplls — 1 10 ms 1.
Table 10-15 Crystal Oscillator Parameters Characteristic Bias Current, low-drive mode Quiescent Current, power-down mode Symbol Min Typ Max Unit IBIASL — 80 110 μA IPD — 0 1 μA 10.8 External Memory Interface Timing The External Memory Interface is designed to access static memory and peripheral devices. Figure 10-5 shows sample timing and parameters that are detailed in Table 10-16.
External Memory Interface Timing The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column of Table 10-16 to make the appropriate selection.
Table 10-16 External Memory Interface Timing (Continued) Wait States Controls Unit WWS,WWSS ns 0.25 + DCAEO WWSH ns -1.780 0.00 RWSH ns tARDD -2.120 1.00 RWSS,RWS ns Valid Input Data Hold after RD Deasserted tDRD 0.00 N/A1 — ns RD Assertion Width tRD 0.279 1.00 RWS ns Address Valid to Input Data Valid tAD -15.723 1.00 -20.642 1.25 + DCAOE RWSS,RWS ns -2.603 0.00 RWSS ns -13.120 1.00 -18.039 1.
Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 (Continued) Characteristic Symbol Typical Min Typical Max Unit See Figure RESET Deassertion to First External Address Output3 tRDA 63T 64T ns 10-6 Edge-sensitive Interrupt Request Width tIRW 1.
A0–A15 First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 10-8 External Level-Sensitive Interrupt Timing IRQA, IRQB tIRI A0–A15 First Interrupt Vector Instruction Fetch Figure 10-9 Interrupt from Wait State Timing IRQA tIW tIF A0–A15 First Instruction Fetch Not IRQA Interrupt Vector Figure 10-10 Recovery from Stop State Using Asynchronous Interrupt Timing 56F8366 Technical Data, Re
Serial Peripheral Interface (SPI) Timing 10.
SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tDH tR tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) LSB in tDI(ref) tDV Master MSB out Bits 14–1 Master LSB out tR tF Figure 10-11 SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in Bits 14–1 tDI tDV(ref) MOSI (Output) tDH Mast
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14–1 tDS Slave LSB out tDV tDI tDH MOSI (Input) MSB in tD Bits 14–1 tDI LSB in Figure 10-13 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) Slave MSB out Bits 14–1 tDS tDV tDH MOSI (Input)
10.11 Quad Timer Timing Table 10-19 Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure PIN 2T + 6 — ns 10-15 Timer input high / low period PINHL 1T + 3 — ns 10-15 Timer output period POUT 1T - 3 — ns 10-15 POUTHL 0.5T - 3 — ns 10-15 Timer input period Timer output high / low period 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design.
Serial Communication Interface (SCI) Timing PPH PPH PPH PPH Phase A (Input) PHL PIN PHL Phase B PHL (Input) PIN PHL Figure 10-16 Quadrature Decoder Timing 10.13 Serial Communication Interface (SCI) Timing Table 10-21 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-17 TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-18 Baud Rate2 1. Parameters listed are guaranteed by design. 2.
TXD SCI receive data pin (Input) TXDPW Figure 10-18 TXD Pulse Width 10.14 Controller Area Network (CAN) Timing Note: CAN is NOT available in the 56F8166 device. Table 10-22 CAN Timing1 Characteristic Baud Rate Bus Wake Up detection Symbol Min Max Unit See Figure BRCAN — 1 Mbps — T WAKEUP 5 — μs 10-19 1. Parameters listed are guaranteed by design CAN_RX CAN receive data pin (Input) T WAKEUP Figure 10-19 Bus Wake Up Detection 10.
JTAG Timing Table 10-23 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK low to TDO data valid tDV — 30 ns 10-21 TCK low to TDO tri-state tTS — 30 ns 10-21 tTRST 2T2 — ns 10-22 TRST assertion time 1. TCK frequency of operation must be less than 1/8 the processor rate. 2.
TRST (Input) tTRST Figure 10-22 TRST Timing Diagram 10.16 Analog-to-Digital Converter (ADC) Parameters Table 10-24 ADC Parameters Characteristic Symbol Min Typ Max Unit VADIN VREFL — VREFH V Resolution RES 12 — 12 Bits Integral Non-Linearity1 INL — +/- 2.4 +/- 3.2 LSB2 Differential Non-Linearity DNL — +/- 0.7 < +1 LSB2 Input voltages Monotonicity GUARANTEED ADC internal clock fADIC 0.
Analog-to-Digital Converter (ADC) Parameters Table 10-24 ADC Parameters (Continued) Characteristic Symbol Min Typ Max Unit Calibration Factor 17 CF1 — — 0.002289 — Calibration Factor 2 CF2 — — –25.6 — — — -60 — dB Vcommon — (VREFH - VREFLO) / 2 — V SNR — 64.6 — db SINAD — 59.1 — db THD — 60.6 — db Spurious Free Dynamic Range SFDR — 61.1 — db Effective Number Of Bits8 ENOB — 9.
Figure 10-23 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDCin = 0.60V and 2.70V Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken on 25 parts: five each from four processing corner lots as well as five from one nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C (giving the 75 data points shown above), for two input DC voltages: 0.60V and 2.70V.
Power Consumption switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential voltage centered about VREFH - VREFH / 2. The switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are additional capacitances associated with the analog input pad, routing, etc.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the IO cell types used on the device reveal that the power-versus-load curve does have a non-zero Y-intercept. Table 10-25 IO Loading Coefficients at 10MHz Intercept Slope PDU08DGZ_ME 1.3 0.11mW / pF PDU04DGZ_ME 1.15mW 0.
56F8366 Package and Pin-Out Information Part 11 Packaging 11.1 56F8366 Package and Pin-Out Information VSS EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2 CAN_RX CAN_TX VPPI TDO TDI TMS TCK TRST VDD_IO TC0 TD1 TD0 ISA2 ISA1 ISA0 EXTBOOT ANB7 ANB6 ANB5 This section contains package and pin-out information for the 56F8366. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP).
Table 11-1 56F8366 144-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8366 Package and Pin-Out Information Table 11-1 56F8366 144-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
11.2 56F8166 Package and Pin-Out Information VSS EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2 NC NC VPPI TDO TDI TMS TCK TRST VDD_IO TC0 GPIOE11 GPIOE10 GPIOC10 GPIOC9 GPIOC8 EXTBOOT ANB7 ANB6 ANB5 This section contains package and pin-out information for the 56F8166. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP).
56F8166 Package and Pin-Out Information Table 11-2 56F8166 144-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
Table 11-2 56F8166 144-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8166 Package and Pin-Out Information 0.20 H B-C D 4X 144 PIN 1 INDEX 0.20 A B-C D 4X 36 TIPS 109 1 108 4X A A E1 C B 4 CL 5 E 7 140X E1/2 36 73 37 72 D NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS B, C AND D TO BE DETERMINED AT DATUM H. 4. THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE SIZE BY A MAXIMUM OF 0.1 mm. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSIONS.
Please see www.freescale.com for the most current case outline. Part 12 Design Considerations 12.
Electrical Design Considerations ΨJT = Thermal characterization parameter (oC)/W PD = Power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
• • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.
Power Distribution and I/O Ring Implementation VDDA_OSC_PLL VDDA_ADC VDD REG VCAP REG I/O ADC CORE OSC VSS VREFH VREFP VREFMID VREFN VREFLO VSSA_ADC Figure 12-1 Power Management Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts.
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