Datasheet

Architecture Block Diagram
56F8366 Technical Data, Rev. 7
Freescale Semiconductor 11
Preliminary
Figure 1-1 System Bus Interfaces
Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
Program
RAM
56800E
Program
Flash
Data RAM
EMI
Data Flash
IPBus
Bridge
Boot
Flash
Flash
Memory
Module
CHIP
TAP
Controller
TAP
Linking
Module
JTAG / EOnCE
5
pab[20:0]
pdb_m[15:0]
cdbw[31:0]
xab1[23:0]
xab2[23:0]
cdbr_m[31:0]
xdb2_m[15:0]
17
16
6
External
JTAG
Port
To Flash
Con trol Logic
IPBus
Data
Address
Control
NOT available on the 56F8166 device.