Datasheet

56F8366 Technical Data, Rev. 7
110 Freescale Semiconductor
Preliminary
5.6.22 IRQ Pending 4 Register (IRQP4)
Figure 5-24 IRQ Pending 4 Register (IRQP4)
5.6.22.1 IRQ Pending (PENDING)—Bits 80–65
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
5.6.23 IRQ Pending 5 Register (IRQP5)
Figure 5-25 IRQ Pending Register 5 (IRQP5)
5.6.23.1 Reserved—Bits 96–86
This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing.
5.6.23.2 IRQ Pending (PENDING)—Bits 81–85
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 85.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
5.6.24 Reserved—Base + 17
5.6.25 Reserved—Base + 18
5.6.26 Reserved
—Base + 19
5.6.27 Reserved—Base + 1A
Base + $15
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
PENDING [80:65]
Write
RESET
1111111111111111
Base + $16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
1 1 1 1 1 1 1 1 1 1 1 1 PENDING[81:85]
Write
RESET
111111111111111 1