Datasheet

External Memory Interface Timing
56F8366 Technical Data, Rev. 7
Freescale Semiconductor 155
Preliminary
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column
of Table 10-16 to make the appropriate selection.
Figure 10-5 External Memory Interface Timing
Note: When multiple lines are given for the same wait state configuration, calculate each and then select the
smallest or most negative.
Table 10-16 External Memory Interface Timing
Characteristic Symbol
Wait States
Configuration
DM
Wait States
Controls
Unit
Address Valid to WR Asserted
t
AWR
WWS=0 -2.076 0.50
WWSS
ns
WWS>0 -1.795 0.75 + DCAOE
WR
Width Asserted to WR
Deasserted
t
WR
WWS=0 -0.094 0.25 + DCAOE
WWS
ns
WWS>0 -0.012 0
Data Out Valid to WR
Asserted
t
DWR
WWS=0 -9.321 0.25 + DCAEO
WWSS
ns
WWS=0 -1.160 0.00
WWS>0 -8.631 0.50
WWS>0 -0.879 0.25 + DCAOE
Valid Data Out Hold Time after WR
Deasserted
t
DOH
-2.086 0.25 + DCAEO WWSH
ns
t
DRD
t
RDD
t
AD
t
DOH
t
DOS
t
DWR
t
RDWR
t
WAC
t
WRRD
t
WR
t
AWR
t
WRWR
t
ARDD
t
RDA
t
RDRD
t
RD
t
ARDA
Data Out Data In
A0-Axx,CS
RD
WR
D0-D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.