Datasheet

Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8366 Technical Data, Rev. 7
Freescale Semiconductor 157
Preliminary
Figure 10-6 Asynchronous Reset Timing
Figure 10-7 External Interrupt Timing (Negative Edge-Sensitive)
RESET Deassertion to First External Address Output
3
t
RDA
63T 64T ns 10-6
Edge-sensitive Interrupt Request Width
t
IRW
1.5T — ns 10-7
IRQA
, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
t
IDM
18T — ns 10-8
t
IDM - FAST
14T —
IRQA
, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
18T — ns 10-8
t
IG - FAST
14T —
Delay from IRQA
Assertion (exiting Wait) to External
Data Memory Access
4
t
IRI
22T — ns 10-9
t
IRI -FAST
18T —
Delay from IRQA
Assertion to External Data Memory
Access (exiting Stop)
t
IF
22T — ns 10-10
t
IF - FAST
18T —
IRQA
Width Assertion to Recover from Stop State
5
t
IW
1.5T — ns 10-10
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2
21
T.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This
is not the minimum required so that the IRQA
interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
(Continued)
Characteristic Symbol
Typical
Min
Typical
Max
Unit See Figure
First Fetch
t
RA
t
RAZ
t
RDA
A0–A15,
D0–D15
RESET
IRQA,
IRQB
t
IRW