Datasheet

56F8366 Technical Data, Rev. 7
42 Freescale Semiconductor
Preliminary
The device’s external memory interface (EMI) can operate much like the 56F80x family’s EMI, or it can
be operated in a mode similar to that used on other products in the 56800E family. Initially, CS0 and CS1
are configured as PS and DS, in a mode compatible with earlier 56800 devices.
Eighteen address lines are required to shadow the first 192K of internal program space when booting
externally for development purposes. Therefore, the entire complement of on-chip memory cannot be
accessed using a 16-bit 56800-compatible address bus. To address this situation, the EMI_MODE pin can
be used to configure four GPIO pins as Address[19:16] upon reset (only one of these pins [A16] is usable
in the 56F8366/56F8166).
The EMI_MODE pin also affects the reset vector address, as provided in Table 4-4. Additional pins must
be configured as address or chip select signals to access addresses at P:$10 and above.
Table 4-3 Changing OMR MA Value During Normal Operation
OMR MA Chip Operating Mode
0 Use internal P-space memory map configuration
1 Use external P-space memory map configuration – If MB = 0 at reset, changing this bit has no
effect.