56F8367/56F8167 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8367 Rev. 9 11/2009 freescale.
Document Revision History Version History Description of Change Rev 0 Pre-release, Alpha customers only Rev 1.0 Initial Public Release Rev 2.0 Added output voltage maximum value and note to clarify in Table 10-1.; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. Clarified value and unit measure for Maximum allowed PD in Table 10-3.
56F8367/56F8167 General Description Note: Features in italics are NOT available in the 56F8167 device.
Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8367/56F8167 Features . . . . . . . . . . . . . 5 Device Description . . . . . . . . . . . . . . . . . . . . 7 Award-Winning Development Environment . 9 Architecture Block Diagram . . . . . . . . . . . . 10 Product Documentation . . . . . . . . . . . . . . . 14 Data Sheet Conventions . . . . . . . . . . . . . . . 14 Part 2: Signal/Connection Descriptions . . . 15 2.1. Introduction . . . . .
6F8367/56F8167 Features Part 1 Overview 1.1 56F8367/56F8167 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
1.1.3 Memory Note: Features in italics are NOT available in the 56F8167 device.
Device Description • • Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) — In the 56F8367, SPI1 can also be used as Quadrature Decoder 1, Quad Timer B or GPIO — In the 56F8167, SPI1 can alternately be used only as GPIO • • • • • • • • 1.1.
1.2.1 56F8367 Features The 56F8367 controller includes 512KB of Program Flash and 32KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 32KB of Data RAM. It also supports program execution from external memory. A total of 32KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas.
Award-Winning Development Environment A key application-specific feature of the 56F8167 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control.
1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8167 device and are shaded in the following figures. The 56F8367/56F8167 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories, the external memory interface and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function.
Architecture Block Diagram 5 JTAG / EOnCE Boot Flash pdb_m[15:0] pab[20:0] Program Flash cdbw[31:0] Program RAM 56800E 24 CHIP TAP Controller TAP Linking Module EMI xab1[23:0] Address 16 Data 10 Control Data RAM xab2[23:0] External JTAG Port Data Flash cdbr_m[31:0] xdb2_m[15:0] IPBus Bridge To Flash Control Logic Flash Memory Module NOT available on the 56F8167 device. IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Memory (FM) Module.
To/From IPBus Bridge Interrupt Controller CLKGEN (OSC/PLL) Low Voltage Interrupt Timer A POR & LVI 4 System POR Quadrature Decoder 0 4 RESET SIM Timer D COP Reset Timer B 4 COP 2 FlexCAN Quadrature Decoder 1 2 FlexCAN2 SPI 1 13 PWMA GPIO A SYNC Output GPIO B 13 PWMB SYNC Output GPIO C GPIO D ch3i GPIO E ch3o ch2i 2 Timer C ch2o GPIO F 4 2 2 ADCB 8 SPI 0 ADCA SCI 0 TEMP_SENSE SCI 1 IPBus NOT available on the 56F8167 device.
Architecture Block Diagram Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
1.5 Product Documentation The documents in Table 1-2 are required for a complete description and proper design with the 56F8367/56F8167 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com.
Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8367 and 56F8167 are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin.
Power Power Power Ground Ground VDD_IO VDDA_OSC_PLL VDDA_ADC VSS VSSA_ADC OCR_DIS Other Supply Ports PLL and Clock *VCAP1 - VCAP4 VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO A0 - A5 (GPIOA8 - 13) A6 - A7 (GPIOE2 - 3) External Address Bus or GPIO External Data Bus A8 - A15 (GPIOA0 - 7) 1 1 1 1 1 1 56F8367 1 4 2 1 1 1 1 1 1 1 1 PWMB0 - 5 ISB0 - 2 (GPIOD10 - 12) FAULTB0 - 3 PWMB ANA0 - 7 VREF ADCA ANB0 - 7 ADCB Temp_Sense Temperature Sense 6 3 GPIOB7 (A23, oscillator_clock) 1 4 WR PS/CS0 (G
Introduction Power VDD_IO Power VDDA_ADC Power Ground VDDA_OSC_PLL Ground VSSA_ADC VSS OCR_DIS *VCAP1 - VCAP4 Other Supply Ports VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO PLL and Clock A0 - A5 (GPIOA8 - 13) A6 - A7 (GPIOE2 - 3) External Address Bus or GPIO A8 - A15 (GPIOA0 - 7) 7 1 1 1 1 6 1 1 1 1 4 2 1 1 1 1 1 1 1 2 GPIOB7 (A23, oscillator_clock) 1 External Bus Control or GPIO WR D7 - D15 (GPIOF0 - 8) 1 1 1 3 7 9 6 3 4 8 5 8 RD PS (CS0, GPIOD8) DS (CS1, GPIOD9) GPIOD0 - 5 (C
2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Note: Signals in italics are NOT available in the 56F8167 device. Note: The 160 Map Ball Grid Array is not available in the 56F8167 device. If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) State During Reset Signal Name Pin No. Ball No. Type VSS 27 J4 Supply VSS — These pins provide ground for chip logic and I/O drivers. VSS 41 K11 VSS 74 G11 VSS 80 E7 VSS 125 J11 VSS 160 E6 VSSA_ADC 115 D12 Supply ADC Analog Ground — This pin supplies an analog ground to the ADC modules.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type XTAL 93 K12 Input/ Output State During Reset Signal Description Chip-driven Crystal Oscillator Output — This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to GND. The input clock can be selected to provide the clock directly to the core.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type A6 17 G1 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Address Bus — A6 - A7 specify two of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A6 - A7 and EMI control signals are tri-stated when the external bus is inactive.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type State During Reset GPIOB0 33 L1 Schmitt Input/ Output Input, pull-up enabled (A16) Output GPIOB1 (A17) 34 GPIOB2 (A18) 35 L2 GPIOB3 (A19) 36 M1 Signal Description Port B GPIO — These four GPIO pins can be programmed as input or output pins. Address Bus — A16 - A19 specify one of the address lines for external program or data memory accesses.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type D0 70 P10 Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Data Bus — D0 - D6 specify part of the data for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), D0–D6 are tri-stated when the external bus is inactive.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type D7 28 K1 Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Data Bus — D7 - D15 specify part of the data for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), D7 - D15 are tri-stated when the external bus is inactive.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type WR 51 L4 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Write Enable — WR is asserted during external memory write cycles. When WR is asserted low, pins D0 - D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type GPIOD0 55 P6 Input/ Output State During Reset Input, pull-up enabled Output (CS2) Signal Description Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. Chip Select — CS2 may be programmed within the EMI module to act as a chip select for specific areas of the external memory map.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type GPIOD2 57 K6 Input/ Output State During Reset Input, pull-up enabled Output (CS4) GPIOD3 (CS5) 58 N7 GPIOD4 (CS6) 59 P7 GPIOD5 (CS7) 60 L7 Signal Description Port D GPIO — These four GPIO pins can be individually programmed as input or output pins.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type TXD1 49 P4 Output (GPIOD6) Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Transmit Data — SCI1 transmit data output Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type TRST 136 D9 Schmitt Input State During Reset Signal Description Input, Test Reset — As an input, a low signal on this pin provides a pulled high reset signal to the JTAG TAP controller. To ensure complete internally hardware reset, TRST should be asserted whenever RESET is asserted.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type INDEX0 157 A1 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index — Quadrature Decoder 0, INDEX input (TA2) Schmitt Input/ Output TA2 — Timer A, Channel 2 (GPOPC6) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is INDEX0.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type MOSI0 148 B6 Input/ Output (GPIOE5) State During Reset In reset, output is disabled, pull-up is enabled Input/ Output Signal Description SPI 0 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type PHASEA1 6 C1 Schmitt Input (TB0) State During Reset Input, pull-up enabled Schmitt Input/ Output (SCLK1) Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1. TB0 — Timer B, Channel 0 Schmitt Input/ Output (GPIOC0) Signal Description SPI 1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type INDEX1 8 E2 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index1 — Quadrature Decoder 1, INDEX input (TB2) Schmitt Input/ Output TB2 — Timer B, Channel 2 (MISO1) Schmitt Input/ Output SPI 1 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) State During Reset Signal Name Pin No. Ball No. Type PWMA0 73 M11 Output PWMA0 - 5 — These are six PWMA outputs.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) State During Reset Signal Name Pin No. Ball No.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type State During Reset TD0 129 B10 Schmitt Input/ Output Input, pull-up enabled (GPIOE10) TD1 (GPIOE11) 130 A10 TD2 (GPIOE12) 131 D10 TD3 (GPIOE13) 132 E10 IRQA 65 K9 IRQB 66 P9 Schmitt Input/ Output Signal Description TD0 - 3— Timer D, Channels 0, 1, 2 and 3 Port E GPIO — These GPIO pins can be individually programmed as input or output pins.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Signal Name Pin No. Ball No. Type EXTBOOT 124 B11 Schmitt Input State During Reset Input, pull-up enabled Signal Description External Boot — This input is tied to VDD to force the device to boot from off-chip memory (assuming that the on-chip Flash memory is not in a secure state). Otherwise, it is tied to ground. For details, see Table 4-4.
Introduction Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the specific OCCS block diagram to reference in the OCCS chapter of the 56F8300 Peripheral User Manual.
start-up. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Registers the OCCS_COHL bit high as well. XTAL EXTAL External Clock VSS Note: When using an external clocking source with this configuration, the input “CLKMODE” should be high and the COHL bit in the OSCTL register should be set to 1. Figure 3-4 Connecting an External Clock Register 3.
4.2 Program Map The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory map configurations that are possible at reset. After reset, the OMR MA bit can be changed and will have an effect on the P-space memory map, as shown in Table 4-3. Changing the OMR MB bit will have no effect.
Interrupt Vector Table Table 4-4 Program Memory Map at Reset Begin/End Address Mode 0 (MA = 0) Mode 11 (MA = 1) Internal Boot External Boot Internal Boot 16-Bit External Address Bus P:$1F FFFF P:$10 0000 P:$0F FFFF P:$05 0000 EMI_MODE = 02,3 16-Bit External Address Bus External Program Memory6 External Program Memory5 External Program Memory5 P:$04 FFFF P:$04 F800 On-Chip Program RAM 4KB P:$04 F7FF P:$04 4000 Reserved 92KB P:$04 3FFF P:$04 0000 Boot Flash 32KB COP Reset Address = 04 0002 Boo
The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part 5.6.11 for the reset value of the VBA. In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions.
Interrupt Vector Table Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + FLEXCAN 26 0-2 P:$34 FLEXCAN Bus Off FLEXCAN 27 0-2 P:$36 FLEXCAN Error FLEXCAN 28 0-2 P:$38 FLEXCAN Wake Up FLEXCAN 29 0-2 P:$3A FLEXCAN Message Buffer Interrupt GPIOF 30 0-2 P:$3C GPIO F GPIOE 31 0-2 P:$3E GPIO E GPIOD 32 0-2 P:$40 GPIO D GPIOC 33 0-2 P:$42 GPIO C GPIOB 34 0-2 P:$44 GPIO B GPIOA 35 0-2 P:$46 GPIO A Peripheral
Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + TMRB 60 0-2 P:$78 Timer B, Channel 0 TMRB 61 0-2 P:$7A Timer B, Channel 1 TMRB 62 0-2 P:$7C Timer B, Channel 2 TMRB 63 0-2 P:$7E Timer B, Channel 3 TMRA 64 0-2 P:$80 Timer A, Channel 0 TMRA 65 0-2 P:$82 Timer A, Channel 1 TMRA 66 0-2 P:$84 Timer A, Channel 2 TMRA 67 0-2 P:$86 Timer A, Channel 3 SCI0 68 0-2 P:$88 SCI 0 Transmitter Empty SCI0 69 0-2 P:$8A
Data Map 4.4 Data Map Note: Data Flash is NOT available on the 56F8167 device.
Program Memory BOOT_FLASH_START + $3FFF BOOT_FLASH_START = $04_0000 PROG_FLASH_START + $03_FFFF Data Memory FM_BASE + $14 32KB Boot FM_BASE + $00 Configure Field Banked Registers Unbanked Registers FM_PROG_MEM_TOP = $01_FFFF DATA_FLASH_START + $3FFF 256KB Program 32KB DATA_FLASH_START + $0000 Note: Data Flash is NOT available in the 56F8167 device.
EOnCE Memory Map 4.
Table 4-9 summarizes base addresses for the set of peripherals on the 56F8367 and 56F8167 devices. Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals. Note: Features in italics are NOT available on the 56F8167 device.
Peripheral Memory Mapped Registers Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number Power Supervisor LVI X:$00 F360 4-36 FM FM X:$00 F400 4-37 FlexCAN FC X:$00 F800 4-38 FlexCAN2 FC2 X:$00 FA00 4-39 Table 4-10 External Memory Integration Registers Address Map (EMI_BASE = $00 F020) Register Acronym Address Offset CSBAR 0 $0 Register Description Chip Select Base Address Register 0 Reset Value 0x0004 = 64K when EXTBOOT =
Table 4-10 External Memory Integration Registers Address Map (Continued) (EMI_BASE = $00 F020) Register Acronym Address Offset Register Description CSTC 2 $12 Chip Select Timing Control Register 2 CSTC 3 $13 Chip Select Timing Control Register 3 CSTC 4 $14 Chip Select Timing Control Register 4 CSTC 5 $15 Chip Select Timing Control Register 5 CSTC 6 $16 Chip Select Timing Control Register 6 CSTC 7 $17 Chip Select Timing Control Register 7 BCR $18 Bus Control Register Reset Value 0x01
Peripheral Memory Mapped Registers Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description Reserved TMRA2_CMP1 $20 Compare Register 1 TMRA2_CMP2 $21 Compare Register 2 TMRA2_CAP $22 Capture Register TMRA2_LOAD $23 Load Register TMRA2_HOLD $24 Hold Register TMRA2_CNTR $25 Counter Register TMRA2_CTRL $26 Control Register TMRA2_SCR $27 Status and Control Register TMRA2_CMPLD1 $28 Comparator Load Register
Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8167 device Register Acronym Address Offset Register Description TMRB0_CNTR $5 Counter Register TMRB0_CTRL $6 Control Register TMRB0_SCR $7 Status and Control Register TMRB0_CMPLD1 $8 Comparator Load Register 1 TMRB0_CMPLD2 $9 Comparator Load Register 2 TMRB0_COMSCR $A Comparator Status and Control Register Reserved TMRB1_CMP1 $10 Compare Register 1 TMRB1_CMP2 $11
Peripheral Memory Mapped Registers Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8167 device Register Acronym Address Offset Register Description TMRB3_LOAD $33 Load Register TMRB3_HOLD $34 Hold Register TMRB3_CNTR $35 Counter Register TMRB3_CTRL $36 Control Register TMRB3_SCR $37 Status and Control Register TMRB3_CMPLD1 $38 Comparator Load Register 1 TMRB3_CMPLD2 $39 Comparator Load Register 2 TMRB3_COMSCR
Table 4-13 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC1_CMPLD2 $19 Comparator Load Register 2 TMRC1_COMSCR $1A Comparator Status and Control Register Reserved TMRC2_CMP1 $20 Compare Register 1 TMRC2_CMP2 $21 Compare Register 2 TMRC2_CAP $22 Capture Register TMRC2_LOAD $23 Load Register TMRC2_HOLD $24 Hold Register TMRC2_CNTR $25 Counter Register TMRC2_CTRL $26 Control Register TMRC2_SCR $27 St
Peripheral Memory Mapped Registers Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8167 device Register Acronym Address Offset Register Description TMRD0_LOAD $3 Load Register TMRD0_HOLD $4 Hold Register TMRD0_CNTR $5 Counter Register TMRD0_CTRL $6 Control Register TMRD0_SCR $7 Status and Control Register TMRD0_CMPLD1 $8 Comparator Load Register 1 TMRD0_CMPLD2 $9 Comparator Load Register 2 TMRD0_COMSCR $A Com
Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8167 device Register Acronym Address Offset Register Description TMRD3_CMP1 $30 Compare Register 1 TMRD3_CMP2 $31 Compare Register 2 TMRD3_CAP $32 Capture Register TMRD3_LOAD $33 Load Register TMRD3_HOLD $34 Hold Register TMRD3_CNTR $35 Counter Register TMRD3_CTRL $36 Control Register TMRD3_SCR $37 Status and Control Register TMRD3_CMPLD1 $38 Comparator Load R
Peripheral Memory Mapped Registers Table 4-15 Pulse Width Modulator A Registers Address Map (Continued) (PWMA_BASE = $00 F140) PWMA is NOT available in the 56F8167 device Register Acronym Address Offset Register Description PWMA_PMPORT $11 Port Register PWMA_PMICCR $12 PWM Internal Correction Control Register Table 4-16 Pulse Width Modulator B Registers Address Map (PWMB_BASE = $00 F160) Register Acronym Address Offset Register Description PWMB_PMCTL $0 Control Register PWMB_PMFCTL $1 Faul
Table 4-17 Quadrature Decoder 0 Registers Address Map (Continued) (DEC0_BASE = $00 F180) Register Acronym Address Offset Register Description DEC0_REV $5 Revolution Counter Register DEC0_REVH $6 Revolution Hold Register DEC0_UPOS $7 Upper Position Counter Register DEC0_LPOS $8 Lower Position Counter Register DEC0_UPOSH $9 Upper Position Hold Register DEC0_LPOSH $A Lower Position Hold Register DEC0_UIR $B Upper Initialization Register DEC0_LIR $C Lower Initialization Register DEC0_
Peripheral Memory Mapped Registers Table 4-19 Interrupt Control Registers Address Map (ITCN_BASE = $00 F1A0) Register Acronym Address Offset Register Description IPR 0 $0 Interrupt Priority Register 0 IPR 1 $1 Interrupt Priority Register 1 IPR 2 $2 Interrupt Priority Register 2 IPR 3 $3 Interrupt Priority Register 3 IPR 4 $4 Interrupt Priority Register 4 IPR 5 $5 Interrupt Priority Register 5 IPR 6 $6 Interrupt Priority Register 6 IPR 7 $7 Interrupt Priority Register 7 IPR 8 $8
Table 4-20 Analog-to-Digital Converter Registers Address Map (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_CR 1 $0 Control Register 1 ADCA_CR 2 $1 Control Register 2 ADCA_ZCC $2 Zero Crossing Control Register ADCA_LST 1 $3 Channel List Register 1 ADCA_LST 2 $4 Channel List Register 2 ADCA_SDIS $5 Sample Disable Register ADCA_STAT $6 Status Register ADCA_LSTAT $7 Limit Status Register ADCA_ZCSTAT $8 Zero Crossing Status Register ADCA_RSLT 0 $9
Peripheral Memory Mapped Registers Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_OFS 0 $21 Offset Register 0 ADCA_OFS 1 $22 Offset Register 1 ADCA_OFS 2 $23 Offset Register 2 ADCA_OFS 3 $24 Offset Register 3 ADCA_OFS 4 $25 Offset Register 4 ADCA_OFS 5 $26 Offset Register 5 ADCA_OFS 6 $27 Offset Register 6 ADCA_OFS 7 $28 Offset Register 7 ADCA_POWER $29 Power Control Regis
Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) (ADCB_BASE = $00 F240) Register Acronym Address Offset Register Description ADCB_LLMT 1 $12 Low Limit Register 1 ADCB_LLMT 2 $13 Low Limit Register 2 ADCB_LLMT 3 $14 Low Limit Register 3 ADCB_LLMT 4 $15 Low Limit Register 4 ADCB_LLMT 5 $16 Low Limit Register 5 ADCB_LLMT 6 $17 Low Limit Register 6 ADCB_LLMT 7 $18 Low Limit Register 7 ADCB_HLMT 0 $19 High Limit Register 0 ADCB_HLMT 1 $1A High Limit Register 1
Peripheral Memory Mapped Registers Table 4-23 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00 F280) Register Acronym Address Offset Register Description SCI0_SCIBR $0 Baud Rate Register SCI0_SCICR $1 Control Register Reserved SCI0_SCISR $3 Status Register SCI0_SCIDR $4 Data Register Table 4-24 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00 F290) Register Acronym Address Offset Register Description SCI1_SCIBR $0 Baud Rate Register SCI1_SC
Table 4-27 Computer Operating Properly Registers Address Map (COP_BASE = $00 F2C0) Register Acronym Address Offset Register Description COPCTL $0 Control Register COPTO $1 Time Out Register COPCTR $2 Counter Register Table 4-28 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00 F2D0) Register Acronym Address Offset Register Description PLLCR $0 Control Register PLLDB $1 Divide-By Register PLLSR $2 Status Register Reserved SHUTDOWN $4 Shutdown Register OSCTL $5 Osci
Peripheral Memory Mapped Registers Table 4-30 GPIOB Registers Address Map (GPIOB_BASE = $00 F300) Register Acronym Address Offset Register Description Reset Value GPIOB_PUR $0 Pull-up Enable Register 0 x 00FF GPIOB_DR $1 Data Register 0 x 0000 GPIOB_DDR $2 Data Direction Register 0 x 0000 GPIOB_PER $3 Peripheral Enable Register 0 x 000F for 20-bit EMI address at reset. 0 x 0000 for all other cases. See Table 4-4 for details.
Table 4-32 GPIOD Registers Address Map (GPIOD_BASE = $00 F320) Register Acronym Address Offset Register Description Reset Value GPIOD_PUR $0 Pull-up Enable Register 0 x 1FFF GPIOD_DR $1 Data Register 0 x 0000 GPIOD_DDR $2 Data Direction Register 0 x 0000 GPIOD_PER $3 Peripheral Enable Register 0 x 1FC0 GPIOD_IAR $4 Interrupt Assert Register 0 x 0000 GPIOD_IENR $5 Interrupt Enable Register 0 x 0000 GPIOD_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOD_IPR $7 Interrupt Pe
Peripheral Memory Mapped Registers Table 4-34 GPIOF Registers Address Map (GPIOF_BASE = $00 F340) Register Acronym Address Offset Register Description Reset Value GPIOF_PUR $0 Pull-up Enable Register 0 x FFFF GPIOF_DR $1 Data Register 0 x 0000 GPIOF_DDR $2 Data Direction Register 0 x 0000 GPIOF_PER $3 Peripheral Enable Register 0 x FFFF GPIOF_IAR $4 Interrupt Assert Register 0 x 0000 GPIOF_IENR $5 Interrupt Enable Register 0 x 0000 GPIOF_IPOLR $6 Interrupt Polarity Register 0
Table 4-36 Power Supervisor Registers Address Map (LVI_BASE = $00 F360) Register Acronym Address Offset Register Description LVI_CONTROL $0 Control Register LVI_STATUS $1 Status Register Table 4-37 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FMCLKD $0 Clock Divider Register FMMCR $1 Module Control Register Reserved FMSECH $3 Security High Half Register FMSECL $4 Security Low Half Register Reserved Reserved FMPROT $10
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8167 device Register Acronym Address Offset Register Description FCCTL0 $3 Control Register 0 Register FCCTL1 $4 Control Register 1 Register FCTMR $5 Free-Running Timer Register FCMAXMB $6 Maximum Message Buffer Configuration Register Reserved FCRXGMASK_H $8 Receive Global Mask High Register FCRXGMASK_L $9 Receive Global Mask Low Register FCRX1
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8167 device Register Acronym Address Offset Register Description FCMB1_DATA $4D Message Buffer 1 Data Register FCMB1_DATA $4E Message Buffer 1 Data Register Reserved FCMB2_CONTROL $50 Message Buffer 2 Control / Status Register FCMB2_ID_HIGH $51 Message Buffer 2 ID High Register FCMB2_ID_LOW $52 Message Buffer 2 ID Low Register FCMB2_DATA $53 Message Buffer 2 Data Register FCMB2_D
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8167 device Register Acronym Address Offset Register Description FCMB5_DATA $6D Message Buffer 5 Data Register FCMB5_DATA $6E Message Buffer 5 Data Register Reserved FCMB6_CONTROL $70 Message Buffer 6 Control / Status Register FCMB6_ID_HIGH $71 Message Buffer 6 ID High Register FCMB6_ID_LOW $72 Message Buffer 6 ID Low Register FCMB6_DATA $73 Mes
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8167 device Register Acronym Address Offset Register Description FCMB9_DATA $8D Message Buffer 9 Data Register FCMB9_DATA $8E Message Buffer 9 Data Register Reserved FCMB10_CONTROL $90 Message Buffer 10 Control / Status Register FCMB10_ID_HIGH $91 Message Buffer 10 ID High Register FCMB10_ID_LOW $92 Message Buffer 10 ID Low Register FCMB10_DATA $93 Message Buffer 10 Data Register
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8167 device Register Acronym Address Offset Register Description Reserved FCMB14_CONTROL $B0 Message Buffer 14 Control / Status Register FCMB14_ID_HIGH $B1 Message Buffer 14 ID High Register FCMB14_ID_LOW $B2 Message Buffer 14 ID Low Register FCMB14_DATA $B3 Message Buffer 14 Data Register FCMB14_DATA $B4 Message Buffer 14 Data Register FCMB14_DAT
Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8167 device Register Acronym Address Offset Register Description FC2RX15MASK_H $C Receive Buffer 15 Mask High Register FC2RX15MASK_L $D Receive Buffer 15 Mask Low Register Reserved FC2STATUS $10 Error and Status Register FC2IMASK1 $11 Interrupt Masks 1 Register FC2IFLAG1 $12 Interrupt Flags 1 Register FC2R/T_ERROR_CNTRS $13 Receive and Transmit Error Counters Register Reserved
Peripheral Memory Mapped Registers Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8167 device Register Acronym Address Offset Register Description FC2MB3_CONTROL $58 Message Buffer 3 Control / Status Register FC2MB3_ID_HIGH $59 Message Buffer 3 ID High Register FC2MB3_ID_LOW $5A Message Buffer 3 ID Low Register FC2MB3_DATA $5B Message Buffer 3 Data Register FC2MB3_DATA $5C Message Buffer 3 Data Register FC2MB3_DATA $5D Mes
Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8167 device Register Acronym Address Offset Register Description FC2MB7_ID_LOW $7A Message Buffer 7 ID Low Register FC2MB7_DATA $7B Message Buffer 7 Data Register FC2MB7_DATA $7C Message Buffer 7 Data Register FC2MB7_DATA $7D Message Buffer 7 Data Register FC2MB7_DATA $7E Message Buffer 7 Data Register Reserved FC2MB8_CONTROL $80 Message Buffer 8 Contro l /Status Register FC2M
Peripheral Memory Mapped Registers Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8167 device Register Acronym Address Offset Register Description FC2MB11_DATA $9C Message Buffer 11 Data Register FC2MB11_DATA $9D Message Buffer 11 Data Register FC2MB11_DATA $9E Message Buffer 11 Data Register Reserved FC2MB12_CONTROL $A0 Message Buffer 12 Control / Status Register FC2MB12_ID_HIGH $A1 Message Buffer 12 ID High Register FC2MB1
Table 4-39 FlexCAN2 Registers Address Map (Continued) (FC2_BASE = $00 FA00) FlexCAN2 is NOT available in the 56F8167 device Register Acronym FC2MB15_DATA Address Offset $BE Register Description Message Buffer 15 Data Register Reserved 4.8 Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program.
Introduction Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and what address to jump in order to service this interrupt. 5.
Table 5-2. Interrupt Priority Encoding IPIC_LEVEL[1:0]1 Current Interrupt Priority Level Required Nested Exception Priority 00 No Interrupt or SWILP Priorities 0, 1, 2, 3 01 Priority 0 Priorities 1, 2, 3 01 Priority 1 Priorities 2, 3 11 Priorities 2 or 3 Priority 3 1. See IPIC field definition in Part 5.6.30.2 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does.
Block Diagram 5.4 Block Diagram any0 Priority Level INT1 Level 0 82->7 Priority Encoder 2->4 Decode 7 INT VAB CONTROL IPIC any3 Level 3 Priority Level 82->7 Priority Encoder 7 IACK SR[9:8] PIC_EN INT82 2->4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ITCN is in this mode by default.
5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers. Table 5-3 ITCN Register Summary (ITCN_BASE = $00F1A0) Register Acronym Base Address + Register Name Section Location $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.
Register Descriptions Add.
5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 15 14 Read 0 0 13 12 BKPT_U0IPL 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STPCNT IPL Write RESET 0 0 0 0 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.1.
Register Descriptions 5.6.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.2.
5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.
Register Descriptions 5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.6 Reserved—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.3.
5.6.4.2 GPIOE Interrupt Priority Level (GPIOE IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.3 GPIOF Interrupt Priority Level (GPIOF IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
Register Descriptions 5.6.4.7 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.8 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.
5.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.4 Reserved—Bits 9–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.5.
Register Descriptions 5.6.6 Interrupt Priority Register 5 (IPR5) Base + $5 Read 15 14 13 DEC1_XIRQ IPL Write RESET 0 0 12 DEC1_HIRQ IPL 0 0 11 10 SCI1_RCV IPL 0 0 9 8 SCI1_RERR IPL 0 0 7 6 0 0 0 0 5 4 SCI1_TIDL IPL 0 0 3 2 SCI1_XMIT IPL 0 0 1 0 SPI0_XMIT IPL 0 0 Figure 5-8 Interrupt Priority Register 5 (IPR5) 5.6.6.1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs.
5.6.6.5 Reserved—Bits 7–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.6.6 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.
Register Descriptions 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.2 Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs.
5.6.7.6 Reserved—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.7.7 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.
Register Descriptions 5.6.8.2 Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.3 Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs.
5.6.8.7 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.8 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.9.3 Reserved—Bits 11–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.
5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.
5.6.10.8 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5. 5.6.
5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0 This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority.
Register Descriptions 5.6.18.1 IRQ Pending (PENDING)—Bits 16–2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.18.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.
5.6.21 IRQ Pending 3 Register (IRQP3) Base + $14 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [64:49] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-23 IRQ Pending 3 Register (IRQP3) 5.6.21.1 IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.
Register Descriptions 5.6.23.2 IRQ Pending (PENDING)—Bits 81–85 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 85. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.24 Reserved—Base + 17 5.6.25 Reserved—Base + 18 5.6.26 Reserved—Base + 19 5.6.27 Reserved—Base + 1A 5.6.28 Reserved—Base + 1B 5.6.29 Reserved—Base + 1C 5.6.
5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled.
Register Descriptions 5.6.32.1 Reserved—Bits 15 - 8 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.32.2 FlexCAN2 Message Buffer Interrupt Priority Level (FlexCAN2_MSGBUF IPL)—Bits 7 - 6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.
5.7 Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 5.7.2 ITCN After Reset After reset, all of the ITCN registers are in their default states.
Overview Part 6 System Integration Module (SIM) 6.1 Overview The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features.
6.3 Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and RESET operation The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the RESET pin is asserted. — COP reset and software reset operation The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed.
Register Descriptions 6.5 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F350) Address Offset Address Acronym Register Name Section Location Base + $0 SIM_CONTROL Control Register 6.5.1 Base + $1 SIM_RSTSTS Reset Status Register 6.5.2 Base + $2 SIM_SCR0 Software Control Register 0 6.5.3 Base + $3 SIM_SCR1 Software Control Register 1 6.5.3 Base + $4 SIM_SCR2 Software Control Register 2 6.5.3 Base + $5 SIM_SCR3 Software Control Register 3 6.5.
Add.
Register Descriptions 6.5.1.2 EMI_MODE (EMI_MODE)—Bit 6 This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset. In addition, this pin can be used as a general purpose input pin after reset.
6.5.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.2.2 Software Reset (SWR)—Bit 5 When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.
Register Descriptions 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01D6. Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 Write RESET Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID) 6.5.
6.5.6.3 CAN—Bit 13 This bit controls the pull-up resistors on the CAN_RX pin. 6.5.6.4 EMI_MODE—Bit 12 This bit controls the pull-up resistors on the EMI_MODE pin. 6.5.6.5 RESET—Bit 11 This bit controls the pull-up resistors on the RESET pin. 6.5.6.6 IRQ—Bit 10 This bit controls the pull-up resistors on the IRQA and IRQB pins. 6.5.6.7 XBOOT—Bit 9 This bit controls the pull-up resistors on the EXTBOOT pin. Note: 6.5.6.
Register Descriptions The upper four bits of the GPIOB register can function as GPIO, [A23:20], or as additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed to operate as peripheral outputs, then the choice between [A23:20] and additional clock outputs is done here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as [A23:20]. This can be changed by altering [A23:20] as shown in Figure 6-9.
• • • • • 00100 = Reserved for factory test—PFLASH even clock 00101 = Reserved for factory test—BFLASH clock 00110 = Reserved for factory test—DFLASH clock 00111 = Oscillator output 01000 = Fout (from OCCS) • • • • • • • • • 01001 = Reserved for factory test—IPB clock 01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL) 01011 = Reserved for factory test—Prescaler clock (from OCCS) 01100 = Reserved for factory test—Postscaler clock (from OCCS) 01101 = Reserved for factory test—SYS_C
Register Descriptions GPIOC_PER Register 0 GPIO Controlled I/O Pad Control 1 SIM_ GPS Register 0 Quad Timer Controlled 1 SPI Controlled Figure 6-10 Overall Control of GPIOC Pads Using SIM_GPS Control Table 6-2 Control of GPIOC Pads Using SIM_GPS Control 1 GPIOC_PER GPIOC_DTR SIM_GPS Quad Timer SCR Register OEN bits Control Registers GPIO Input 0 0 — — GPIO Output 0 1 — — Quad Timer Input / Quad Decoder Input 2 1 — 0 0 Quad Timer Output / Quad Decoder Input 3 1 — 0 1 SPI in
GPIOD_PER Register GPIO Controlled 0 I/O Pad Control 1 SIM_ GPS Register EMI Controlled 0 CAN2 Controlled 1 Figure 6-11 Overall Control of GPIOD Pads Using SIM_GPS Control Table 6-3 Control of GPIOD Pads Using SIM_GPS Control 1 GPIOD_PER GPIOD_DDR SIM_GPS Control Registers GPIO Input 0 0 — GPIO Output 0 1 — EMI I/O 1 — 0 EMI CSn pins are always outputs CAN2 1 — 1 CAN2_TX is always an output CAN2_RX is always an input Pin Function Comments 1.
Register Descriptions 6.5.8.2 GPIOD1 (D1)—Bit 5 This bit selects the alternate function for GPIOD1. • • 0 = CS3 1 = CAN2_RX 6.5.8.3 • • GPIOD0 (D0)—Bit 4 0 = CS2 1 = CAN2_TX 6.5.8.4 GPIOC3 (C3)—Bit 3 This bit selects the alternate function for GPIOC3. • 0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the 56F8300 Peripheral User Manual) 1 = SS1 • 6.5.8.5 GPIOC2 (C2)—Bit 2 This bit selects the alternate function for GPIOC2.
6.5.9.1 External Memory Interface Enable (EMI)—Bit 15 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.2 Analog-to-Digital Converter B Enable (ADCB)—Bit 14 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
Register Descriptions 6.5.9.9 Quad Timer B Enable (TMRB)—Bit 7 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.10 Quad Timer A Enable (TMRA)—Bit 6 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL) The I/O Short Address Location registers are used to specify the memory referenced via the I/O short address mode. The I/O short address mode allows the instruction to specify the lower six bits of address; the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure 6-14.
Clock Generation Overview Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 Read ISAL[21:6] Write RESET 1 1 1 1 1 1 1 1 1 Figure 6-16 I/O Short Address Location Low Register (SIM_ISAL) 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.5.
6.7 Power Down Modes Overview The 56F8367/56F8167 operate in one of three power-down modes as shown in Table 6-3. Table 6-4 Clock Operation in Power Down Modes Mode Core Clocks Peripheral Clocks Description Run Active Active Device is fully functional Wait Core and memory clocks disabled Active Peripherals are active and can produce interrupts if they have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation.
Resets The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E system clock must be set equal to the oscillator output. Some applications require the 56800E STOP/WAIT instructions be disabled.
of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module specification, the device will disable external P-space accesses restricting code execution to internal memory, disable EXTBOOT=1 mode, and disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Blocking Mechanisms The 56F8367/56F8167 have several operating functional and test modes.
Flash Access Blocking Mechanisms The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control the period of the clock used for timed events in the FM erase algorithm. This register must be set with appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300 Peripheral User Manual for more details on setting this register value.
EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8 = FM_CLKDIV[6] = 1. Using the following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of 181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively.
Configuration 8.3 Configuration There are six GPIO ports defined on the 56F8367/56F8167. The width of each port and the associated peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is shown in Table 8-3.
Table 8-2 56F8167 GPIO Ports Configuration (Continued) GPIO Port Port Width Available Pins in 56F8167 E 14 14 2 pins - SCI0 2 pins - EMI Address pins 4 pins - SPI0 2 pins - TMRC 4 pins - Dedicated GPIO SCI0 EMI Address SPI0 TMRC GPIO F 16 16 16 pins - EMI Data EMI Data Peripheral Function Reset Function Table 8-3 GPIO External Signals Map Pins in italics are NOT available in the 56F8167 device GPIO Port GPIO Bit Reset Function Functional Signal Package Pin 0 Peripheral A8 19 1 Perip
Configuration Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8167 device GPIO Port GPIOB 1This GPIO Bit Reset Function Functional Signal Package Pin 0 GPIO1 A16 33 1 GPIO1 A17 34 2 GPIO1 A18 35 3 GPIO1 A19 36 4 GPIO A20 / Prescaler_clock 37 5 GPIO A21 / SYS_CLK 46 6 GPIO A22 / SYS_CLK2 47 7 GPIO A23 / Oscillator_Clock 48 is a function of the EMI_MODE, EXTBOOT, and Flash security settings at reset.
Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8167 device GPIO Port GPIOD GPIO Bit Reset Function Functional Signal Package Pin 0 GPIO CS2 / CAN2_TX 55 1 GPIO CS3 / CAN2_RX 56 2 GPIO CS4 57 3 GPIO CS5 58 4 GPIO CS6 59 5 GPIO CS7 60 6 Peripheral TXD1 49 7 Peripheral RXD1 50 8 Peripheral PS / CS0 53 9 Peripheral DS / CS1 54 10 Peripheral ISB0 61 11 Peripheral ISB1 63 12 Peripheral ISB2 64 0 Peripheral TXD
56F8367 Information Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8167 device GPIO Port GPIO Bit Reset Function Functional Signal Package Pin 0 Peripheral D7 28 1 Peripheral D8 29 2 Peripheral D9 30 3 Peripheral D10 32 4 Peripheral D11 149 5 Peripheral D12 150 6 Peripheral D13 151 7 Peripheral D14 152 8 Peripheral D15 153 9 Peripheral D0 70 10 Peripheral D1 71 11 Peripheral D2 83 12 Peripheral D3 86 13 P
Part 10 Specifications 10.1 General Characteristics The 56F8367/56F8167 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such sytems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.
General Characteristics Note: The 56F8167 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8167 device. Table 10-1 Absolute Maximum Ratings (VSS = VSSA_ADC = 0) Characteristic Supply Voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Symbol Notes VDD_IO VDDA_ADC, VREFH VREFH must be less than or equal to VDDA_ADC VDDA_OSC_PLL Min Max Unit -0.3 4.0 V -0.3 4.0 V -0.3 4.0 V VDD_CORE OCR_DIS is High -0.3 3.
Table 10-2 56F8367/56F8167 ElectroStatic Discharge (ESD) Protection Characteristic Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 500 — — V Table 10-3 Thermal Characteristics6 Characteristic Comments Value Value 160-pin LQFP 160MAPBGA Symbol Unit Notes Junction to ambient Natural convection RθJA 38.5 39.90 °C/W 2 Junction to ambient (@1m/sec) RθJMA 35.4 46.
General Characteristics Note: The 56F8167 device is guaranteed to 40HMz and specified to meet Industrial requirements only; CAN is NOT available on the 56F8167 device. Table 10-4 Recommended Operating Conditions (VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL ) Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Symbol Notes VDD_IO VDDA_ADC VREFH VREFH must be less than or Min Typ Max Unit 3 3.3 3.6 V 3 3.3 3.6 V 3 3.3 3.6 V 2.25 2.5 2.
10.2 DC Electrical Characteristics Note: The 56F8167 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8167 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions;see Table 10-4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage VOH 2.4 — — V IOH = IOHmax Output Low Voltage VOL — — 0.4 V IOL = IOLmax IIH Pin Groups 1, 2, 5, 6, 9 — 0 +/- 2.5 μA VIN = 3.0V to 5.
DC Electrical Characteristics μA 0 –10 –30 –50 –70 –90 0 1 2 3 Volts Figure 10-1 Maximum Current — Schmitt Input DC Response –40 °C, 3.6 V Table 10-6 Power-On Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1.75 1.8 1.9 V LVI, 2.5 volt Supply, trip point1 VEI2.5 — 2.14 — V LVI, 3.3 volt supply, trip point2 VEI3.3 — 2.7 — V Bias Current I bias — 110 130 μA 1. When VDD_CORE drops below VEI2.5, an interrupt is generated. 2.
Table 10-7 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Enabled (OCR_DIS = Low) Mode Stop1 IDD_IO1 IDD_ADC IDD_OSC_PLL 6mA 0μA 165μA Test Conditions • 8MHz Device Clock • All peripheral clocks are off • ADC powered off • PLL powered off Stop2 5.1mA 0μA 155μA • External Clock is off • All peripheral clocks are off • ADC powered off • PLL powered off 1. No Output Switching 2.
DC Electrical Characteristics Table 10-9. Regulator Parameters Characteristic Symbol Min Typical Max Unit Loaded Output Voltage (200 mA load) VRL 2.25 — 2.75 V Line Regulation @ 250 mA load (VDD33 ranges from 3.0 to 3.6) VR 2.25 — 2.75 V Short Circuit Current ( output shorted to ground) Iss — — 700 mA I bias — 5.8 7 mA Ipd — 0 2 μA TRSC — — 30 minutes Bias Current Power-down Current Short-Circuit Tolerance (output shorted to ground) Table 10-10.
Table 10-11 Temperature Sense Parametrics Characteristics Symbol Min Typical Max Unit VDDA_ADC 3.0 3.3 3.6 V Supply Current - OFF IDD-OFF — — 10 μA Supply Current - ON IDD-ON — — 250 μA Accuracy3,1 from -40°C to 150°C Using VTS = mT + VTS0 TACC -6.7 0 6.7 °C Resolution4, 5,1 RES — 0.104 — °C / bit Supply Voltage 1. Includes the ADC conversion of the analog Temperature Sense voltage. 2.
Flash Memory Characteristics Data2 Valid Data1 Valid Data1 Data3 Valid Data2 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 10-3 Signal States 10.4 Flash Memory Characteristics Table 10-12 Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 Tprog 20 — — μs Erase time2 Terase 20 — — ms Tme 100 — — ms Mass erase time 1. There is additional overhead which is part of the programming sequence.
VIH External Clock 90% 50% 10% 90% 50% 10% tfall tPW tPW VIL trise Note: The midpoint is VIL + (VIH – VIL)/2. Figure 10-4 External Clock Timing 10.6 Phase Locked Loop Timing Table 10-14 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 8.4 MHz PLL output frequency2 (fOUT) fop 160 — 260 MHz PLL stabilization time3 -40° to +125°C tplls — 1 10 ms 1.
External Memory Interface Timing Table 10-15 Crystal Oscillator Parameters Characteristic Symbol Min Typ Max Unit IPD — 0 1 μA Quiescent Current, power-down mode 10.8 External Memory Interface Timing The External Memory Interface is designed to access static memory and peripheral devices. Figure 10-5 shows sample timing and parameters that are detailed in Table 10-16.
A0-Axx,CS tRD tARDD tRDA tARDA tRDRD RD tWAC tAWR tWRWR tWRRD tWR tRDWR WR tDWR tDOH tRDD tDOS tAD tDRD Data Out D0-D15 Data In Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 10-5 External Memory Interface Timing Note: When multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative.
Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-16 External Memory Interface Timing (Continued) Characteristic Symbol Wait States Configuration D M Wait States Controls Unit Address Valid to RD Deasserted tARDD -2.120 1.00 RWSS,RWS ns Valid Input Data Hold after RD Deasserted tDRD 0.00 N/A1 — ns RD Assertion Width tRD 0.279 1.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 Characteristic IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine Delay from IRQA Assertion (exiting Wait) to External Data Memory Access4 Delay from IRQA Assertion to External Data Memory Access (exiting Stop) IRQA Width Assertion to Recover from Stop State5 Symbol Typical Min Typical Max Unit See Figure tIG 18T — ns 10-8 tIG - FAST 14T — tIRI 22T —
Reset, Stop, Wait, Mode Select, and Interrupt Timing A0–A15, PS, DS, RD, WR First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 10-8 External Level-Sensitive Interrupt Timing IRQA, IRQB tIRI A0–A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 10-9 Interrupt from Wait State Timing tIW IRQA tIF A0–A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector
10.10 Serial Peripheral Interface (SPI) Timing Table 10-18 SPI Timing1 Characteristic Symbol Cycle time Master Slave Min Max Unit 50 50 — — ns ns — 25 — — ns ns — 100 — — ns ns 17.6 25 — — ns ns 24.1 25 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.
Serial Peripheral Interface (SPI) Timing SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) LSB in tDI(ref) tDV Master MSB out Bits 14–1 Master LSB out tR tF Figure 10-11 SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in Bits 14–1 t
SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14–1 tDS Slave LSB out tDV tDI tDH MOSI (Input) MSB in tD Bits 14–1 tDI LSB in Figure 10-13 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) tD tF Slave MSB out Bits 14–1 tDS tDV Slave LSB out tDI tDH MOSI (Input) MSB in Bits 14
Quad Timer Timing 10.11 Quad Timer Timing Table 10-19 Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure PIN 2T + 6 — ns 10-15 Timer input high / low period PINHL 1T + 3 — ns 10-15 Timer output period POUT 1T - 3 — ns 10-15 POUTHL 0.5T - 3 — ns 10-15 Timer input period Timer output high / low period 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design.
PPH PPH PPH PPH Phase A (Input) PHL PIN PHL Phase B PHL (Input) PIN PHL Figure 10-16 Quadrature Decoder Timing 10.13 Serial Communication Interface (SCI) Timing Table 10-21 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-17 TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-18 Baud Rate2 1. Parameters listed are guaranteed by design. 2.
Controller Area Network (CAN) Timing 10.14 Controller Area Network (CAN) Timing Note: CAN is not available in the 56F8167 device. Table 10-22 CAN Timing1 Characteristic Symbol Min Max Unit See Figure BRCAN — 1 Mbps — T WAKEUP 5 — μs 10-19 Baud Rate Bus Wake Up detection 1. Parameters listed are guaranteed by design CAN_RX CAN receive data pin (Input) T WAKEUP Figure 10-19 Bus Wakeup Detection 10.
1/fOP tPW tPW VM VM VIH TCK (Input) VIL VM = VIL + (VIH – VIL)/2 Figure 10-20 Test Clock Input Timing Diagram TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 10-21 Test Access Port Timing Diagram TRST (Input) tTRST Figure 10-22 TRST Timing Diagram 56F8367 Technical Data, Rev.
Analog-to-Digital Converter (ADC) Parameters 10.16 Analog-to-Digital Converter (ADC) Parameters Table 10-24 ADC Parameters Characteristic Symbol Min Typ Max Unit VADIN VREFL — VREFH V Resolution RES 12 — 12 Bits Integral Non-Linearity1 INL — +/- 2.4 +/- 3.2 LSB2 Differential Non-Linearity DNL — +/- 0.7 < +1 LSB2 Input voltages Monotonicity GUARANTEED ADC internal clock fADIC 0.
Table 10-24 ADC Parameters (Continued) Characteristic Symbol Min Typ Max Unit SINAD — 59.1 — db THD — 60.6 — db Spurious Free Dynamic Range SFDR — 61.1 — db Effective Number Of Bits8 ENOB — 9.6 — Bits Signal-to-noise plus distortion ratio Total Harmonic Distortion 1. INL measured from Vin = .1VREFH to Vin = .9VREFH 10% to 90% Input Signal Range 2. LSB = Least Significant Bit 3. ADC clock cycles 4. Assumes each voltage reference pin is bypassed with 0.
Analog-to-Digital Converter (ADC) Parameters Figure 10-23 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDCin = 0.60V and 2.70V Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error.
10.17 Equivalent Circuit for ADC Inputs Figure 10-24 illustrates the ADC input circuit during sample & hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to VREFH - VREFH / 2, while the other charges to the analog input voltage.
Power Consumption C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the IO cell types used on the device reveal that the power-versus-load curve does have a non-zero Y-intercept.
Part 11 Packaging Note: The 160 Map Ball Grid Array is not available in the 56F8167 device. 11.1 56F8367 Package and Pin-Out Information ANB7 ANB6 ANB5 EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2 CAN_RX CAN_TX VPP1 TDO TDI TMS TCK TRST TC1 VDD_IO TC0 TD3 TD2 TD1 TD0 ISA2 ISA1 ISA0 VSS EXTBOOT VSS This section contains package and pin-out information for the 56F8367. This device comes in a 160-pin Low-profile Quad Flat Pack (LQFP) and 160 Map Ball Grid Array.
56F8367 Package and Pin-Out Information Table 11-1 56F8367 160-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
Table 11-1 56F8367 160-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8367 Package and Pin-Out Information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 D12 D11 SCLK0 VPP1 TMS TC0 TD1 ISA0 ANB7 ANB5 ANB4 D13 MOSI0 CAN_RX TDI TC1 TD0 EXTBOOT ANB6 ANB3 ANB1 A INDEX0 PHASEA0 B TXD0 EMI_ HOME0 PHASEB0 MODE C PHASEA1 VPP2 A0 D14 PHASEB1 RXD0 CLKO MISO0 SS0 CAN_TX TDO TCK TRST TD2 A1 A2 VDD_IO VSS VSS VCAP2 VDD_IO TD3 ISA1 ANB2 ANB0 VDDA_ADC D ISA2 VSSA_ADC VREFP VREFH E HOME1 INDEX1 TEMP_ VREFLO SENSE ANA7 VREFMID F A4
Table 11-2 56F8367 -160 MAPBGA Package Identification by Pin Number Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No.
56F8367 Package and Pin-Out Information Table 11-2 56F8367 -160 MAPBGA Package Identification by Pin Number (Continued) Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No.
D X LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA Y M K NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. E MILLIMETERS DIM MIN MAX A 1.32 1.75 A1 0.27 0.47 A2 1.18 REF b 0.35 0.65 D 15.
56F8167 Package and Pin-Out Information 11.2 56F8167 Package and Pin-Out Information ANB7 ANB6 ANB5 VSS EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2* NC NC VPP1 TDO TDI TMS TCK TRST TC1 VDD_IO TC0 GPIOE13 GPIOE12 GPIOE11 GPIOE10 GPIOC10 GPIOC9 GPIOC8 VSS EXTBOOT This section contains package and pin-out information for the 56F8167. This device comes in a 160-pin Low-profile Quad Flat Pack (LQFP).
Table 11-3 56F8167 160-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8167 Package and Pin-Out Information Table 11-3 56F8167 160-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
160X 0.20 C A-B D D b GG D 2 c1 D c 6 SECTION G-G E 2 E1 2 E E1 B A (b) D1 2 D1 4X 0.20 H A-B D DETAIL F 0.08 C e e/2 156X C SEATING PLANE 4X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED WHERE THE LEADS EXIT THE PLASTIC BODY AT DATUM PLANE H. 4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE.
Thermal Design Considerations Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJΑ x PD) where: TA = Ambient temperature for the package (oC) RθJΑ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
Power Distribution and I/O Ring Implementation • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 13-1 Ordering Information Part Supply Voltage Package Type Pin Count Frequency (MHz) MC56F8367 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 160 MC56F8167 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) MC56F8367 3.0–3.
Power Distribution and I/O Ring Implementation THIS PAGE INTENTIONALLY LEFT BLANK 56F8367 Technical Data, Rev.
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