Datasheet

Register Descriptions
56F8367 Technical Data, Rev. 9
Freescale Semiconductor 121
Preliminary
Figure 6-10 Overall Control of GPIOC Pads Using SIM_GPS Control
Two Input/Output pins associated with GPIOD can function as GPIO, EMI (default peripheral) or CAN2
(NOT available on the 56F8167 device) signals. GPIO is the default and is enabled/disabled via the
GPIOD_PER, as shown in Figure 6-11 and Table 6-3. When GPIOD[1:0] are programmed to operate as
peripheral input/output, then the choice between EMI and CAN2 inputs/outputs is made here in the GPS.
Table 6-2 Control of GPIOC Pads Using SIM_GPS Control
1
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is
used for each pin.
Pin Function
Control Registers
Comments
GPIOC_PER GPIOC_DTR
SIM_GPS
Quad Timer
SCR Register
OEN bits
GPIO Input 0 0 — —
GPIO Output 0 1 — —
Quad Timer Input / Quad
Decoder Input
2
2. Reset configuration
1 — 0 0 See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of timer inputs based on the
Quad Decoder mode configuration.
Quad Timer Output / Quad
Decoder Input
3
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
1— 0 1
SPI input 1 — 1 — See SPI controls for determining the direction
of each of the SPI pins.
SPI output 1 — 1 —
GPIOC_PER Register
GPIO Controlled
I/O
Pad Control
SIM_ GPS Register
Quad Timer Controlled
SPI Controlled
0
1
0
1