Datasheet

Configuration
56F8367 Technical Data, Rev. 9
Freescale Semiconductor 133
Preliminary
8.3 Configuration
There are six GPIO ports defined on the 56F8367/56F8167. The width of each port and the associated
peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is
shown in Table 8-3.
Table 8-1 56F8367 GPIO Ports Configuration
GPIO
Port
Port
Width
Available
Pins in
56F8367
Peripheral Function Reset Function
A14 14
14 pins - EMI Address pins
EMI Address
B8 8
8 pins - EMI Address pins
EMI Address
C11 11
4 pins -DEC1 / TMRB / SPI1
4 pins -DEC0 / TMRA
3 pins -PWMA current sense
DEC1 / TMRB
DEC0 / TMRA
PWMA current sense
D13 13
6 pins - EMI CSn
2 pins - SCI1
2 pins - EMI CSn
3 pins -PWMB current sense
EMI Chip Selects
SCI1
EMI Chip Selects
PWMB current sense
E14 14
2 pins - SCI0
2 pins - EMI Address pins
4 pins - SPI0
2 pins - TMRC
4 pins - TMRD
SCI0
EMI Address
SPI0
TMRC
TMRD
F16 16
16 pins - EMI Data
EMI Data
Table 8-2 56F8167 GPIO Ports Configuration
GPIO
Port
Port
Width
Available
Pins in
56F8167
Peripheral Function Reset Function
A14 14
14 pins - EMI Address pins
EMI Address
B8 8
8 pins - EMI Address pins
EMI Address
C11 11
4 pins - SPI1
4 pins - DEC0 / TMRA
3 pins - Dedicated GPIO
SPI1
DEC0 / TMRA
GPIO
D13 13
6 pins - EMI CSn
2 pins - SCI1
2 pins - EMI CSn
3 pins -PWMB current sense
EMI Chip Selects
SCI1
EMI Chip Selects
PWMB current sense