Datasheet

56F8367 Technical Data, Rev. 9
144 Freescale Semiconductor
Preliminary
Stop1
6mA 0μA165μA
• 8MHz Device Clock
• All peripheral clocks are off
• ADC powered off
• PLL powered off
Stop2
5.1mA 0μA155μA
• External Clock is off
• All peripheral clocks are off
• ADC powered off
• PLL powered off
1. No Output Switching
2. Includes Processor Core current supplied by internal voltage regulator
Table 10-8 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Disabled (OCR_DIS = High)
Mode
I
DD_Core
I
DD_IO
1
1. No Output Switching
I
DD_ADC
I
DD_OSC_PLL
Test Conditions
RUN1_MAC
150mA 13μA50mA 2.5mA
• 60MHz Device Clock
• All peripheral clocks are enabled
• All peripherals running
• Continuous MAC instructions with
fetches from Data RAM
• ADC powered on and clocked
Wait3
86mA 13μA70μA2.5mA
• 60MHz Device Clock
• All peripheral clocks are enabled
• ADC powered off
Stop1
950μA13μA0μA165μA
• 8MHz Device Clock
• All peripheral clocks are off
• ADC powered off
• PLL powered off
Stop2
100μA13μA0μA155μA
• External Clock is off
• All peripheral clocks are off
• ADC powered off
• PLL powered off
Table 10-9. Regulator Parameters
Characteristic Symbol Min Typical Max Unit
Unloaded Output Voltage
(0mA Load)
V
RNL
2.25 — 2.75 V
Table 10-7 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
Mode
I
DD_IO
1
I
DD_ADC
I
DD_OSC_PLL
Test Conditions