Datasheet

Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8367 Technical Data, Rev. 9
Freescale Semiconductor 151
Preliminary
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Address Valid to RD Deasserted
t
ARDD
-2.120 1.00 RWSS,RWS
ns
Valid Input Data Hold after RD
Deasserted
t
DRD
0.00
N/A
1
—
ns
RD Assertion Width
t
RD
0.279 1.00 RWS
ns
Address Valid to Input Data Valid
t
AD
-15.723 1.00
RWSS,RWS
ns
-20.642 1.25 + DCAOE
Address Valid to RD Asserted
t
ARDA
-2.603 0.00 RWSS ns
RD
Asserted to Input Data Valid
t
RDD
-13.120 1.00
RWSS,RWS
ns
-18.039 1.25 + DCAOE
WR
Deasserted to RD Asserted
t
WRRD
-2.135 0.25 + DCAEO
WWSH,RWSS
ns
RD
Deasserted to RD Asserted
t
RDRD
-0.483
2
0.00
RWSS,RWSH
MDAR
3, 4
ns
WR
Deasserted to WR Asserted
t
WRWR
WWS=0 -1.608 0.75 + DCAEO
WWSS, WWSH ns
WWS>0 -0.918 1.00
RD Deasserted to WR Asserted
t
RDWR
WWS=0 -0.096 0.50
RWSH, WWSS,
MDAR
3
ns
WWS>0 0.084 0.75 + DCAOE
1. N/A since device captures data before it deasserts RD
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is active in this calculation only when the chip select changes.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
Characteristic Symbol
Typical
Min
Typical
Max
Unit See Figure
RESET
Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
—21ns10-6
Minimum RESET
Assertion Duration t
RA
16T — ns 10-6
RESET
Deassertion to First External Address
Output
3
t
RDA
63T 64T ns 10-6
Edge-sensitive Interrupt Request Width t
IRW
1.5T — ns 10-7
IRQA
, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
t
IDM
18T — ns 10-8
t
IDM
- FAST 14T —
Table 10-16 External Memory Interface Timing (Continued)
Characteristic
Symbol
Wait States
Configuration
DM
Wait States
Controls
Unit