Datasheet

56F8367 Technical Data, Rev. 9
20 Freescale Semiconductor
Preliminary
XTAL 93 K12 Input/
Output
Chip-driven Crystal Oscillator Output — This output connects the internal
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for
the on-chip PLL.
CLKO 3 D3 Output In reset,
output is
disabled
Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock and
postscaler clock. Other signals are also available for test
purposes.
See Part 6.5.7 for details.
A0
(GPIOA8)
154 C3 Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus — A0 - A5 specify six of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A0 - A5 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
A1
(GPIOA9)
10 E3
A2
(GPIOA10)
11 E4
A3
(GPIOA11)
12 F2
A4
(GPIOA12)
13 F1
A5
(GPIOA13)
14 F3
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal
Name
Pin
No.
Ball No. Type
State
During
Reset
Signal Description