Datasheet

Signal Pins
56F8367 Technical Data, Rev. 9
Freescale Semiconductor 21
Preliminary
A6
(GPIOE2)
17 G1 Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus — A6 - A7 specify two of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A6 - A7 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
Port E GPIO — These two GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOE_PUR register.
Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.
A7
(GPIOE3)
18 G3
A8
(GPIOA0)
19 G2 Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus— A8 - A15 specify eight of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A8 - A15 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
Port A GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
A9
(GPIOA1)
20 H1
A10
(GPIOA2)
21 H2
A11
(GPIOA3)
22 H4
A12
(GPIOA4)
23 H3
A13
(GPIOA5)
24 J1
A14
(GPIOA6)
25 J2
A15
(GPIOA7)
26 J3
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal
Name
Pin
No.
Ball No. Type
State
During
Reset
Signal Description