Datasheet

Signal Pins
56F8367 Technical Data, Rev. 9
Freescale Semiconductor 27
Preliminary
GPIOD2
(CS4
)
57 K6 Input/
Output
Output
Input,
pull-up
enabled
Port D GPIO — These four GPIO pins can be individually
programmed as input or output pins.
Chip Select — CS4 - CS7 may be programmed within the EMI
module to act as chip selects for specific areas of the external
memory map.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS4
- CS7 are tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOD_PUR register.
Example: GPIOD2, clear bit 2 in the GPIOD_PUR register.
GPIOD3
(CS5)
58 N7
GPIOD4
(CS6
)
59 P7
GPIOD5
(CS7)
60 L7
TXD0
(GPIOE0)
4 B1 Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Transmit Data — SCI0 transmit data output
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
RXD0
(GPIOE1)
5 D2 Input
Input/
Output
Input,
pull-up
enabled
Receive Data — SCI0 receive data input
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal
Name
Pin
No.
Ball No. Type
State
During
Reset
Signal Description