Datasheet

56F8367 Technical Data, Rev. 9
50 Freescale Semiconductor
Preliminary
Table 4-9 summarizes base addresses for the set of peripherals on the 56F8367 and 56F8167 devices.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Note: Features in italics are NOT available on the 56F8167 device.
Table 4-9 Data Memory Peripheral Base Address Map Summary
Peripheral Prefix Base Address Table Number
External Memory Interface EMI X:$00 F020 4-10
Timer A TMRA X:$00 F040 4-11
Timer B TMRB X:$00 F080 4-12
Timer C TMRC X:$00 F0C0 4-13
Timer D TMRD X:$00 F100 4-14
PWM A PWMA X:$00 F140 4-15
PWM B PWMB X:$00 F160 4-16
Quadrature Decoder 0 DEC0 X:$00 F180 4-17
Quadrature Decoder 1 DEC1 X:$00 F190 4-18
ITCN ITCN X:$00 F1A0 4-19
ADC A ADCA X:$00 F200 4-20
ADC B ADCB X:$00 F240 4-21
Temperature Sensor TSENSOR X:$00 F270 4-22
SCI #0 SCI0 X:$00 F280 4-23
SCI #1 SCI1 X:$00 F290 4-24
SPI #0 SPI0 X:$00 F2A0 4-25
SPI #1 SPI1 X:$00 F2B0 4-26
COP COP X:$00 F2C0 4-27
PLL, OSC CLKGEN X:$00 F2D0 4-28
GPIO Port A GPIOA X:$00 F2E0 4-29
GPIO Port B GPIOB X:$00 F300 4-30
GPIO Port C GPIOC X:$00 F310 4-31
GPIO Port D GPIOD X:$00 F320 4-32
GPIO Port E GPIOE X:$00 F330 4-33
GPIO Port F GPIOF X:$00 F340 4-34
SIM SIM X:$00 F350 4-35