Datasheet

Peripheral Memory Mapped Registers
56F8367 Technical Data, Rev. 9
Freescale Semiconductor 51
Preliminary
Power Supervisor LVI X:$00 F360 4-36
FM FM X:$00 F400 4-37
FlexCAN FC X:$00 F800 4-38
FlexCAN2 FC2 X:$00 FA00 4-39
Table 4-10 External Memory Integration Registers Address Map
(EMI_BASE = $00 F020)
Register Acronym Address Offset Register Description Reset Value
CSBAR 0 $0
Chip Select Base Address Register 0 0x0004 = 64K when EXTBOOT = 0 or
EMI_MODE = 0
0x0008 = 1M when EMI_MODE = 1
(Selects entire program space for
SC0)
CSBAR 1 $1
Chip Select Base Address Register 1 0x0004 = 64K when EMI_MODE = 0
0x0008 = 1M when EMI_MODE = 1
(Selects A0 - 19 addressable data
space for CS1)
CSBAR 2 $2
Chip Select Base Address Register 2
CSBAR 3 $3
Chip Select Base Address Register 3
CSBAR 4 $4
Chip Select Base Address Register 4
CSBAR 5 $5
Chip Select Base Address Register 5
CSBAR 6 $6
Chip Select Base Address Register 6
CSBAR 7 $7
Chip Select Base Address Register 7
CSOR 0 $8
Chip Select Option Register 0 0x5FCB programmed for chip select
for program space, word wide, read
and write, 11 waits
CSOR 1 $9
Chip Select Option Register 1 0x5FAB programmed for chip select
for data space, word wide, read and
write, 11 waits
CSOR 2 $A
Chip Select Option Register 2
CSOR 3 $B
Chip Select Option Register 3
CSOR 4 $C
Chip Select Option Register 4
CSOR 5 $D
Chip Select Option Register 5
CSOR 6 $E
Chip Select Option Register 6
CSOR 7 $F
Chip Select Option Register 7
CSTC 0 $10
Chip Select Timing Control Register 0
CSTC 1 $11
Chip Select Timing Control Register 1
Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued)
Peripheral Prefix Base Address Table Number