Datasheet

56F8367 Technical Data, Rev. 9

52 Freescale Semiconductor

Preliminary

CSTC 2 $12

Chip Select Timing Control Register 2

CSTC 3 $13

Chip Select Timing Control Register 3

CSTC 4 $14

Chip Select Timing Control Register 4

CSTC 5 $15

Chip Select Timing Control Register 5

CSTC 6 $16

Chip Select Timing Control Register 6

CSTC 7 $17

Chip Select Timing Control Register 7

BCR $18

Bus Control Register 0x016B sets the default number of

wait states to 11 for both read and

write accesses

Table 4-11 Quad Timer A Registers Address Map

(TMRA_BASE = $00 F040)

TMRA0_CMP1 $0 Compare Register 1

TMRA0_CMP2 $1 Compare Register 2

TMRA0_CAP $2 Capture Register

TMRA0_LOAD $3 Load Register

TMRA0_HOLD $4 Hold Register

TMRA0_CNTR $5 Counter Register

TMRA0_CTRL $6 Control Register

TMRA0_SCR $7 Status and Control Register

TMRA0_CMPLD1 $8 Comparator Load Register 1

TMRA0_CMPLD2 $9 Comparator Load Register 2

TMRA0_COMSCR $A Comparator Status and Control Register

Reserved

TMRA1_CMP1 $10 Compare Register 1

TMRA1_CMP2 $11 Compare Register 2

TMRA1_CAP $12 Capture Register

TMRA1_LOAD $13 Load Register

TMRA1_HOLD $14 Hold Register

TMRA1_CNTR $15 Counter Register

TMRA1_CTRL $16 Control Register

TMRA1_SCR $17 Status and Control Register

TMRA1_CMPLD1 $18 Comparator Load Register 1

TMRA1_CMPLD2 $19 Comparator Load Register 2

TMRA1_COMSCR $1A Comparator Status and Control Register

Table 4-10 External Memory Integration Registers Address Map (Continued)

(EMI_BASE = $00 F020)