Datasheet

Peripheral Memory Mapped Registers

56F8367 Technical Data, Rev. 9

Freescale Semiconductor 67

Preliminary

Table 4-30 GPIOB Registers Address Map

(GPIOB_BASE = $00 F300)

GPIOB_PUR $0 Pull-up Enable Register 0 x 00FF

GPIOB_DR $1 Data Register 0 x 0000

GPIOB_DDR $2 Data Direction Register 0 x 0000

GPIOB_PER $3 Peripheral Enable Register 0 x 000F for 20-bit EMI

address at reset.

0 x 0000 for all other cases.

See Table 4-4 for details.

GPIOB_IAR $4 Interrupt Assert Register 0 x 0000

GPIOB_IENR $5 Interrupt Enable Register 0 x 0000

GPIOB_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOB_IPR $7 Interrupt Pending Register 0 x 0000

GPIOB_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOB_PPMODE $9 Push-Pull Mode Register 0 x 0000

GPIOB_RAWDATA $A Raw Data Input Register —

Table 4-31 GPIOC Registers Address Map

(GPIOC_BASE = $00F310)

GPIOC_PUR $0 Pull-up Enable Register 0 x 07FF

GPIOC_DR $1 Data Register 0 x 0000

GPIOC_DDR $2 Data Direction Register 0 x 0000

GPIOC_PER $3 Peripheral Enable Register 0 x 07FF

GPIOC_IAR $4 Interrupt Assert Register 0 x 0000

GPIOC_IENR $5 Interrupt Enable Register 0 x 0000

GPIOC_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOC_IPR $7 Interrupt Pending Register 0 x 0000

GPIOC_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOC_PPMODE $9 Push-Pull Mode Register 0 x 07FF

GPIOC_RAWDATA $A Raw Data Input Register —