Datasheet

56F8367 Technical Data, Rev. 9

68 Freescale Semiconductor

Preliminary

Table 4-32 GPIOD Registers Address Map

(GPIOD_BASE = $00 F320)

GPIOD_PUR $0 Pull-up Enable Register 0 x 1FFF

GPIOD_DR $1 Data Register 0 x 0000

GPIOD_DDR $2 Data Direction Register 0 x 0000

GPIOD_PER $3 Peripheral Enable Register 0 x 1FC0

GPIOD_IAR $4 Interrupt Assert Register 0 x 0000

GPIOD_IENR $5 Interrupt Enable Register 0 x 0000

GPIOD_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOD_IPR $7 Interrupt Pending Register 0 x 0000

GPIOD_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOD_PPMODE $9 Push-Pull Mode Register

GPIOD_RAWDATA $A Raw Data Input Register —

Table 4-33 GPIOE Registers Address Map

(GPIOE_BASE = $00 F330)

GPIOE_PUR $0 Pull-up Enable Register 0 x 3FFF

GPIOE_DR $1 Data Register 0 x 0000

GPIOE_DDR $2 Data Direction Register 0 x 0000

GPIOE_PER $3 Peripheral Enable Register 0 x 3FFF

GPIOE_IAR $4 Interrupt Assert Register 0 x 0000

GPIOE_IENR $5 Interrupt Enable Register 0 x 0000

GPIOE_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOE_IPR $7 Interrupt Pending Register 0 x 0000

GPIOE_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOE_PPMODE $9 Push-Pull Mode Register 0 x 3FFF

GPIOE_RAWDATA $A Raw Data Input Register —