Datasheet

MOTOROLA MC68332
20 MC68332TS/D
3.2.2 System Protection Control Register
The system protection control register controls system monitor functions, software watchdog clock
prescaling, and bus monitor timing. This register can be written only once following power-on or reset,
but can be read at any time.
SWE — Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
SWP — Software Watchdog Prescale
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. The following ta-
ble gives the ratio for each combination of SWP and SWT bits.
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] — Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the following table.
SYPCR —System Protection Control Register $YFFA21
15
8 7 6 5 4 3 2 1 0
NOT USED SWE SWP SWT HME BME BMT
RESET:
1 MODCLK 0 0 0 0 0 0
SWP SWT Ratio
000
2
9
001
2
11
010
2
13
011
2
15
100
2
18
101
2
20
110
2
22
111
2
24
BMT Bus Monitor Time-out Period
00 64 System Clocks
01 32 System Clocks
10 16 System Clocks
11 8 System Clocks
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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