Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PQFP 132 (24.13x24.13) 32-Bit 16 MHz I/O number 15

MC68332 MOTOROLA

MC68332TS/D 57

5.2.9 Frequency Measurement (FQM)

FQM counts the number of input pulses to a TPU channel during a user-defined window period. The

function has single shot and continuous modes. No pulses are lost between sample windows in contin-

uous mode. The user selects whether to detect pulses on the rising or falling edge. This function is in-

tended for high speed measurement; measurement of slow pulses with noise rejection can be made

with PTA.

5.2.10 Hall Effect Decode (HALLD)

This function decodes the sensor signals from a brushless motor, along with a direction input from the

CPU, into a state number. The function supports two- or three-sensor decoding. The decoded state

number is written into a COMM channel, which outputs the required commutation drive signals. In ad-

dition to brushless motor applications, the function can have more general applications, such as decod-

ing “option” switches.

5.3 Programmer's Model

The TPU control register address map occupies 512 bytes. The “Access” column in the TPU address

map below indicates which registers are accessible only at the supervisor privilege level and which can

be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the

TPUMCR.

Y = M111, where M represents the logic state of the module mapping (MM) bit in the SIMCR.

Table 22 TPU Address Map

Access Address 15 8 7 0

S $YFFE00 TPU MODULE CONFIGURATION REGISTER (TPUMCR)

S $YFFE02 TEST CONFIGURATION REGISTER (TCR)

S $YFFE04 DEVELOPMENT SUPPORT CONTROL REGISTER (DSCR)

S $YFFE06 DEVELOPMENT SUPPORT STATUS REGISTER (DSSR)

S $YFFE08 TPU INTERRUPT CONFIGURATION REGISTER (TICR)

S $YFFE0A CHANNEL INTERRUPT ENABLE REGISTER (CIER)

S $YFFE0C CHANNEL FUNCTION SELECTION REGISTER 0 (CFSR0)

S $YFFE0E CHANNEL FUNCTION SELECTION REGISTER 1 (CFSR1)

S $YFFE10 CHANNEL FUNCTION SELECTION REGISTER 2 (CFSR2)

S $YFFE12 CHANNEL FUNCTION SELECTION REGISTER 3 (CFSR3)

S/U $YFFE14 HOST SEQUENCE REGISTER 0 (HSQR0)

S/U $YFFE16 HOST SEQUENCE REGISTER 1 (HSQR1)

S/U $YFFE18 HOST SERVICE REQUEST REGISTER 0 (HSRR0)

S/U $YFFE1A HOST SERVICE REQUEST REGISTER 1 (HSRR1)

S $YFFE1C CHANNEL PRIORITY REGISTER 0 (CPR0)

S $YFFE1E CHANNEL PRIORITY REGISTER 1 (CPR1)

S $YFFE20 CHANNEL INTERRUPT STATUS REGISTER (CISR)

S $YFFE22 LINK REGISTER (LR)

S $YFFE24 SERVICE GRANT LATCH REGISTER (SGLR)

S $YFFE26 DECODED CHANNEL NUMBER REGISTER (DCNR)

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