Datasheet

MOTOROLA MC68332
30 MC68332TS/D
Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write
strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single
DSACK generator is shared by all circuits. Multiple chip selects assigned to the same address and con-
trol must have the same number of wait states.
Chip selects can also be synchronized with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select sig-
nals are active low. Refer to the following block diagram of a single chip-select circuit.
Figure 9 Chip-Select Circuit Block Diagram
The following table lists allocation of chip-selects and discrete outputs on the pins of the MCU.
Pin Chip Select Discrete Outputs
CSBOOT
CSBOOT —
BR
CS0 —
BG
CS1 —
BGACK
CS2 —
FC0 CS3
PC0
FC1 CS4
PC1
FC2 CS5
PC2
ADDR19 CS6
PC3
ADDR20 CS7
PC4
ADDR21 CS8
PC5
ADDR22 CS9
PC6
ADDR23 CS10
ECLK
CHIP SEL BLOCK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
BASE ADDRESS REGISTER
TIMING
AND
CONTROL
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
AVEC
DSACK
PIN
BUS CONTROL
INTERNAL
SIGNALS
ADDRESS
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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