Datasheet

MOTOROLA MC68332
34 MC68332TS/D
CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap opera-
tions from peripheral memory devices.
The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode selected (chip-select assertion determined by internal or external bus con-
trol signals)
1 = Synchronous mode selected (chip-select assertion synchronized with ECLK signal)
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
The DSACK field is not used in synchronous mode because a bus cycle is only performed as a syn-
chronous operation. When a match condition occurs on a chip select programmed for synchronous op-
eration, the chip select signals the EBI that an ECLK cycle is pending.
BYTE — Upper/Lower Byte Option
This field is used only when the chip-select 16-bit port option is selected in the pin assignment register.
The following table lists upper/lower byte options.
R/W — Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
Refer to the following table for options available.
STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address
strobe causes chip select to be asserted synchronized with address strobe. Selecting data strobe caus-
es chip select to be asserted synchronized with data strobe.
CSORBT —Chip-Select Option Register Boot ROM $YFFA4A
15 14 13 12 11 10 9 6 5 4 3 1 0
MODE BYTE R/W STRB DSACK SPACE IPL AVEC
RESET:
0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0
CSOR[10:0] —Chip-Select Option Registers $YFFA4E–$YFFA76
15 14 13 12 11 10 9 6 5 4 3 1 0
MODE BYTE R/W STRB DSACK SPACE IPL AVEC
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Byte Description
00 Disable
01 Lower Byte
10 Upper Byte
11 Both Bytes
R/W
Description
00 Reserved
01 Read Only
10 Write Only
11 Read/Write
Fr
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Freescale Semiconductor, Inc.
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