Datasheet

MC68332 MOTOROLA
MC68332TS/D 71
6.5 QSPI Submodule
The QSPI submodule communicates with external devices through a synchronous serial bus. The QSPI
is fully compatible with the serial peripheral interface (SPI) systems found on other Motorola products.
A block diagram of the QSPI is shown below.
Figure 14 QSPI Block Diagram
6.5.1 QSPI Pins
Seven pins are associated with the QSPI. When not needed for a QSPI application, they can be con-
figured as general-purpose I/O pins. The PCS0/SS pin can function as a peripheral chip select output,
slave select input, or general-purpose I/O. Refer to the following table for QSPI input and output pins
and their functions.
QSPI BLOCK
CONTROL
REGISTERS
END QUEUE
POINTER
QUEUE
POINTER
STATUS
REGISTER
DELAY
COUNTER
COMPARATOR
PROGRAMMABLE
LOGIC ARRAY
80-BYTE
QSPI RAM
CHIP SELECT
COMMAND
DONE
4
4
3
BAUD RATE
GENERATOR
PCS [3:1]
PCS0/SS
MISO
MOSI
SCK
M
S
M
S
8/16-BIT SHIFT REGISTER
Rx/Tx DATA REGISTER
MSB LSB
4
QUEUE CONTROL
BLOCK
CONTROL
LOGIC
ADDRESS
REGISTER
4
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...