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M68HC08

Microcontrollers

freescale.com

MC68HC908GZ16

MC68HC908GZ8

Data Sheet

MC68HC908GZ16

Rev. 4.0

10/2006

Summary of content (314 pages)

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MC68HC908GZ16 MC68HC908GZ8 Data Sheet M68HC08 Microcontrollers MC68HC908GZ16 Rev. 4.0 10/2006 freescale.
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MC68HC908GZ16 MC68HC908GZ8 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
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Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level February, 2003 N/A Page Number(s) Description Initial release N/A Reorganized to meet latest publication standards for M68HC08 Family documentation N/A Added Table 1-1. Summary of Device Variations 19 Figure 5-2.
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List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Chapters MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Table of Contents Chapter 1 General Description 1.1 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 1.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.
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4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.6 4.7 4.7.1 4.7.2 4.7.3 4.8 4.8.1 4.8.2 4.8.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 6.7 6.7.1 6.7.2 6.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . .
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Chapter 10 Low-Power Modes 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Analog-to-Digital Converter (ADC). . . . . . . . . . . . .
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Table of Contents Chapter 11 Low-Voltage Inhibit (LVI) 11.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.5 11.6 11.6.1 11.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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12.13.3 12.13.4 12.13.5 12.13.6 12.13.7 12.13.8 12.13.9 12.13.10 12.13.11 12.13.12 12.13.13 MSCAN08 Bus Timing Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Receiver Interrupt Enable Register . . . . . . . . . . . . . . . . . .
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Table of Contents 14.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2.1 Software Interrupt (SWI) Instruction . . . . . . . . .
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.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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18.4 18.5 18.6 18.6.1 18.6.2 18.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBM Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 20.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 General Description 1.1 Introduction The MC68HC908GZ16 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 0. Table 1-1.
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General Description • • • • • • • • • • • • • • • • • • • • • • • • • System protection features: – Optional computer operating properly (COP) reset – Low-voltage detection with optional reset and selectable trip points for 3.3-V and 5.
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MCU Block Diagram • • Specific features of the MC68HC908GZ16 in 32-pin LQFP are: – Port A is only 4 bits: PTA0–PTA3; 4-pin keyboard interrupt (KBI) module – Port B is only 6 bits: PTB0–PTB5; 6-channel ADC module – Port C is only 2 bits: PTC0–PTC1; shared with MSCAN08 module – Port D is only 7 bits: PTD0–PTD6; shared with SPI, TIM1, and TIM2 modules – Port E is only 2 bits: PTE0–PTE1; shared with ESCI module Specific features of the MC68HC908GZ16 in 48-pin LQFP are: – Port A is 8 bits: PTA0–PTA7; 8-pin KB
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General Description INTERNAL BUS PORTA PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE DDRD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE 1–8 MHz OSCILLATOR SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE MEMORY MAP MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA PTE5–PTE2 PTE1/RxD PTE0/TxD 2-CHANNEL TIMER INTERFACE MODULE 2 COMPUTER OPERATING PROPERLY MODULE VDDAD/VREFL PORTB CLOCK GENERATOR MODULE VDDAD/VREFH PORTC
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CGMXFC VSSA VDDA PTC1/CANRX PTC0/CANTX PTA3/KBD3 30 29 28 27 26 25 1 OSC2 RST 31 32 OSC1 Pin Assignments 24 PTA2/KBD2 PTD1/MISO 6 19 PTB5/AD5 PTD2/MOSI 7 18 PTB4/AD4 PTD3/SPSCK 8 17 PTB3/AD3 16 VDDAD/VREFH PTB2/AD2 20 15 5 PTB1/AD1 PTD0/SS 14 VSSAD/VREFL PTB0/AD0 21 13 4 PTD6/T2CH0 IRQ 12 PTA0/KBD0 PTD5/T1CH1 22 11 3 PTD4/T1CH0 PTE1/RxD 10 PTA1/KBD1 VDD 23 9 2 VSS PTE0/TxD CGMXFC VSSA VDDA PTC1/CANRX PTC0/CANTX PTA7/KBD7 PTA6/KBD6 PTA5/K
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General Description 1.5 Pin Functions Descriptions of the pin functions are provided here. 1.5.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible.
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Pin Functions 1.5.5 CGM Power Supply Pins (VDDA and VSSA) VDDA and VSSA are the power supply pins for the analog portion of the clock generator module (CGM). Decoupling of these pins should be as per the digital supply. See Chapter 4 Clock Generator Module (CGM). 1.5.6 External Filter Capacitor Pin (VCGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Chapter 4 Clock Generator Module (CGM). 1.5.
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General Description These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. 1.5.12 Port E I/O Pins (PTE5–PTE2, PTE1/RxD, and PTE0/TxD) PTE5–PTE0 are general-purpose, bidirectional I/O port pins. PTE1 and PTE0 can also be programmed to be enhanced serial communications interface (ESCI) pins. PTE5–PTE2 are only available on the 48-pin LQFP package.
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Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 15,872 bytes of user FLASH memory • 1024 bytes of random-access memory (RAM) • 406 bytes of FLASH programming routines read-only memory (ROM) • 44 bytes of user-defined vectors • 350 bytes of monitor ROM 2.2 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset.
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Memory $0000 ↓ I/O REGISTERS 64 BYTES $003F $0040 ↓ RAM 1024 BYTES $043F $0440 ↓ UNIMPLEMENTED 192 BYTES $04FF $0500 ↓ MSCAN08 CONTROL AND MESSAGE BUFFER 128 BYTES UNIMPLEMENTED 5760 BYTES INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 BREAK ADDRESS REGISTER HIGH (BRKH) $FE0A BREAK ADDRESS REGISTER LOW (BRKL) $FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR)
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Input/Output (I/O) Section Addr. $0000 Register Name Port A Data Register Read: (PTA) Write: See page 158. Reset: $0001 Port B Data Register Read: (PTB) Write: See page 160. Reset: $0002 Port C Data Register Read: (PTC) Write: See page 162. Reset: $0003 $0004 Port D Data Register Read: (PTD) Write: See page 164. Reset: Data Direction Register A Read: (DDRA) Write: See page 158. Reset: $0005 Data Direction Register B Read: (DDRB) Write: See page 161.
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Memory Addr. $000C $000D $000E $000F Register Name Data Direction Register E Read: (DDRE) Write: See page 168. Reset: $0011 $0012 Port C Input Pullup Enable Read: Register (PTCPUE) Write: See page 164.
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Input/Output (I/O) Section Addr. $0018 $0019 $001A $001B Register Name ESCI Data Register Read: (SCDR) Write: See page 204. Reset: ESCI Baud Rate Register Read: (SCBR) Write: See page 204. Reset: Keyboard Status Read: and Control Register Write: (INTKBSCR) See page 107. Reset: Keyboard Interrupt Enable Read: Register (INTKBIER) Write: See page 108.
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Memory Addr. $0024 $0025 $0026 $0027 Register Name Timer 1 Counter Modulo Read: Register Low (T1MODL) Write: See page 267. Reset: Timer 1 Channel 0 Status and Read: Control Register (T1SC0) Write: See page 267. Reset: Timer 1 Channel 0 Read: Register High (T1CH0H) Write: See page 270. Reset: Timer 1 Channel 0 Read: Register Low (T1CH0L) Write: See page 270. Reset: Timer 1 Channel 1 Status and Read: $0028 Control Register (T1SC1) Write: See page 267.
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Input/Output (I/O) Section Addr. Register Name Bit 7 Timer 2 Channel 0 Status and Read: $0030 Control Register (T2SC0) Write: See page 267. Reset: CH0F $0031 $0032 Timer 2 Channel 0 Read: Register High (T2CH0H) Write: See page 270. Reset: Timer 2 Channel 0 Read: Register Low (T2CH0L) Write: See page 270. Reset: Timer 2 Channel 1 Status and Read: $0033 Control Register (T2SC1) Write: See page 267. Reset: $0034 $0035 $0036 Timer 2 Channel 1 Read: Register High (T2CH1H) Write: See page 270.
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Memory Addr. $003C $003D $003E $003F Register Name Bit 7 6 5 4 3 2 1 Bit 0 COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 1 1 1 1 1 ADC Data High Register Read: (ADRH) Write: See page 55. Reset: 0 0 0 0 0 0 AD9 AD8 ADC Data Low Register Read: (ADRL) Write: See page 55. Reset: AD7 AD2 AD1 AD0 ADC Status and Control Read: Register (ADSCR) Write: See page 53. Reset: ADC Clock Register Read: (ADCLK) Write: See page 57.
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Input/Output (I/O) Section Addr. Register Name $0560 ↓ $056F MSCAN08 Transmit Buffer 1 See page 137. MSC08 transmitter buffer 1 Refer to 12.12 Programmer’s Model of Message Storage $0570 ↓ $057F MSCAN08 Transmit Buffer 2 See page 137. MSC08 transmitter buffer 2 Refer to 12.12 Programmer’s Model of Message Storage $FE00 Bit 7 Break Status Register Read: (BSR) Write: See page 275.
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Memory Addr. Register Name Break Address Register Low Read: $FE0A (BRKL) Write: See page 274. Reset: $FE0B $FE0C $FF7E Break Status and Control Read: Register (BRKSCR) Write: See page 274. Reset: Read: LVI Status Register (LVISR) Write: See page 119. Reset: FLASH Block Protect Read: Register (FLBPR)(3) Write: See page 44.
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Input/Output (I/O) Section . Table 2-1.
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Memory 2.5 Random-Access Memory (RAM) Addresses $0040 through $043F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code.
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FLASH Memory (FLASH) The address ranges for the user memory and vectors are: • $C000–$FDFF; user memory • $FE08; FLASH control register • $FF7E; FLASH block protect register • $FFD4–$FFFF; these locations are reserved for user-defined interrupt and reset vectors Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. NOTE A security feature prevents viewing of the FLASH contents.(1) 2.6.
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Memory 2.6.3 FLASH Page Erase Operation Use this step-by-step procedure to erase a page (64 bytes) of FLASH memory to read as logic 1. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 44-byte user interrupt vectors area also forms a page. Any FLASH memory page can be erased alone. 1. Set the ERASE bit, and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3.
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FLASH Memory (FLASH) 2.6.4 FLASH Mass Erase Operation Use this step-by-step procedure to erase entire FLASH memory to read as logic 1: 1. Set both the ERASE bit, and the MASS bit in the FLASH control register. 2. Read from the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS (minimum 10 μs) 5. Set the HVEN bit. 6. Wait for a time, tMErase (minimum 4 ms) 7. Clear the ERASE and MASS bits.
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Memory 10. 11. 12. 13. Clear the PGM bit.(1) Wait for a time, tNVH (minimum 5 μs). Clear the HVEN bit. After time, tRCV (typical 1 μs), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed. NOTE Programming and erasing of FLASH locations can not be performed by code being executed from the same FLASH array. NOTE While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
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FLASH Memory (FLASH) Algorithm for programming a row (32 bytes) of FLASH memory 1 2 3 SET PGM BIT READ THE FLASH BLOCK PROTECT REGISTER WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 5 6 7 8 WAIT FOR A TIME, tNVS SET HVEN BIT WAIT FOR A TIME, tPGS WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG COMPLETED PROGRAMMING THIS ROW? Y N 10 11 CLEAR PGM BIT WAIT FOR A TIME, tNVH Note: The time between each FLASH address change (step 7 to st
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Memory 2.6.6 FLASH Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. This protection is done by using of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected.
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FLASH Memory (FLASH) The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be $XX00, $XX40, $XX80, and $XXC0 (64 bytes page boundaries) within the FLASH memory. 16-BIT MEMORY ADDRESS START ADDRESS OF FLASH 1 BLOCK PROTECT 1 FLBPR VALUE 0 0 0 0 0 0 Figure 2-6. FLASH Block Protect Start Address Table 2-2.
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Memory MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 10-bit analog-to-digital converter (ADC). 3.2 Features Features of the ADC module include: • Eight channels with multiplexed input • Linear successive approximation with monotonicity • 10-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock • Left or right justified result • Left justified sign data mode 3.
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Analog-to-Digital Converter (ADC) INTERNAL BUS 1–8 MHz OSCILLATOR VDDAD/VREFH VDDAD/VREFL PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE PTE5–PTE2 PTE1/RxD PTE0/TxD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) 2-CHANNEL TIMER INT
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Functional Description INTERNAL DATA BUS READ DDRBx WRITE DDRBx DISABLE DDRBx RESET WRITE PTBx PTBx PTBx ADC CHANNEL x READ PTBx DISABLE ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC ADC VOLTAGE IN (VADIN) CHANNEL SELECT ADCH4–ADCH0 ADC CLOCK COCO CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV2–ADIV0 ADICLK Figure 3-2. ADC Block Diagram 3.3.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $3FF (full scale).
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Analog-to-Digital Converter (ADC) 3.3.3 Conversion Time Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency. Conversion time = 16 to 17 ADC cycles ADC frequency Number of bus cycles = conversion time × bus frequency 3.3.4 Conversion In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
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Monotonicity is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL is present. NOTE Quantization error is affected when only the most significant eight bits are used as a result. See Figure 3-3.
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Analog-to-Digital Converter (ADC) 3.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the WAIT instruction. 3.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
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I/O Registers 3.7.4 ADC Voltage Reference Low Pin (VREFL) The ADC analog portion uses VREFL as its lower voltage reference pin. By default, connect the VREFH pin to the same voltage potential as VSS. External filtering is often necessary to ensure a clean VREFL for good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values.
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Analog-to-Digital Converter (ADC) ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH4–ADCH0 — ADC Channel Select Bits ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels.
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I/O Registers 3.8.2 ADC Data Register High and Data Register Low 3.8.2.1 Left Justified Mode In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read.
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Analog-to-Digital Converter (ADC) 3.8.2.3 Left Justified Signed Data Mode In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read.
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I/O Registers 3.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: Read: Write: Reset: $003F Bit 7 6 5 4 3 2 1 ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 R 0 0 0 0 0 1 0 R = Reserved = Unimplemented Bit 0 0 0 Figure 3-9. ADC Clock Register (ADCLK) ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock.
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Analog-to-Digital Converter (ADC) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Chapter 4 Clock Generator Module (CGM) 4.1 Introduction This section describes the clock generator module. The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
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Clock Generator Module (CGM) OSCILLATOR (OSC) OSC2 CGMXCLK (TO: SIM, TIMTB15A, ADC) OSC1 SIMOSCEN (FROM SIM) OSCSTOPENB (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRCLK CLOCK SELECT CIRCUIT BCS VDDA CGMXFC ÷2 A CGMOUT B S* (TO SIM) *WHEN S = 1, VSSA CGMOUT = B SIMDIV2 (FROM SIM) VPR1–VPR0 VRS7–VRS0 VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER PHASE DETECTOR CGMVCLK PLL ANALOG AUTOMATIC MODE CONTROL LOCK DETECTOR LOCK AUTO ACQ INTERRUPT CONTROL PLLIE CGMINT (TO SIM) PLLF MUL11–MUL0
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Functional Description 4.3.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency.
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Clock Generator Module (CGM) frequency, fRCLK. The circuit determines the mode of the PLL and the lock condition based on this comparison. 4.3.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency.
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Functional Description The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 4.8 Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL).
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Clock Generator Module (CGM) In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Chapter 21 Electrical Specifications. After choosing N, the actual bus frequency can be determined using equation in 2 above. 4. Select a VCO frequency multiplier, N.
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Functional Description 11. Program the PLL registers accordingly: a. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. b. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. If using a 1–8 MHz reference, the PMSL register must be reprogrammed from the reset value before enabling the pll. c. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
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Clock Generator Module (CGM) 4.3.9 CGM External Connections In its typical configuration, the CGM requires external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 4-2. Figure 4-2 shows only the logical representation of the internal components and may not represent actual circuitry.
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I/O Signals 4.4 I/O Signals The following paragraphs describe the CGM I/O signals. 4.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 4.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 4.4.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 4-2.
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Clock Generator Module (CGM) 4.4.8 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 4-2 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors.
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CGM Registers Addr. Register Name Bit 7 $0036 PLL Control Register Read: (PCTL) Write: See page 69. Reset: $0037 PLL Bandwidth Control Read: Register (PBWC) Write: See page 71. Reset: $0038 $0039 $003A PLLF PLLIE 0 PLL VCO Select Range Read: Register (PMRS) Write: See page 73.
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Clock Generator Module (CGM) PLLIE — PLL Interrupt Enable Bit This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF — PLL Interrupt Flag Bit This read-only bit is set whenever the LOCK bit toggles.
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CGM Registers VPR1 and VPR0 — VCO Power-of-Two Range Select Bits These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction with L controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when the PLLON bit is set. Reset clears these bits. (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and 4.5.5 PLL VCO Range Select Register.) Table 4-4.
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Clock Generator Module (CGM) LOCK — Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written a 0. Reset clears the LOCK bit.
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CGM Registers 4.5.4 PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider. Address: Read: Write: Reset: $0038 Bit 7 6 5 4 3 2 1 Bit 0 MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 0 1 0 0 0 0 0 0 Figure 4-7. PLL Multiplier Select Register Low (PMSL) NOTE For applications using 1–8 MHz reference frequencies this register must be reprogrammed before enabling the PLL.
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Clock Generator Module (CGM) NOTE Verify that the value of the PMRS register is appropriate for the given reference and VCO clock frequencies before enabling the PLL. See 4.3.6 Programming the PLL for detailed instructions on selecting the proper value for these control bits. VRS7–VRS0 — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and 4.5.1 PLL Control Register.
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Special Modes 4.7 Special Modes The WAIT instruction puts the MCU in low power-consumption standby modes. 4.7.1 Wait Mode The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power. Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is immediately available at WAIT exit.
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Clock Generator Module (CGM) Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered.
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Acquisition/Lock Time Specifications CGMXFC CGMXFC RF1 CF2 CF CF1 VSSA VSSA (A) (B) Figure 4-9. PLL Filter Table 4-5. Example Filter Component Values fRCLK CF1 CF2 RF1 CF 1 MHz 8.2 nF 820 pF 2k 18 nF 2 MHz 4.7 nF 470 pF 2k 6.8 nF 3 MHz 3.3 nF 330 pF 2k 5.6 nF 4 MHz 2.2 nF 220 pF 2k 4.7 nF 5 MHz 1.8 nF 180 pF 2k 3.9 nF 6 MHz 1.5 nF 150 pF 2k 3.3 nF 7 MHz 1.2 nF 120 pF 2k 2.7 nF 8 MHz 1 nF 100 pF 2k 2.2 nF MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Clock Generator Module (CGM) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2.
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Configuration Register (CONFIG) Address: Read: Write: Reset: $001F Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD 0 0 0 0 See note 0 0 0 Note: LVI5OR3 bit is only reset via POR (power-on reset). Figure 5-2. Configuration Register 1 (CONFIG1) MSCANEN— MSCAN08 Enable Bit Setting the MSCANEN enables the MSCAN08 module and allows the MSCAN08 to use the PTC0/PTC1 pins.
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Functional Description LVISTOP — LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI). 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module.
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Configuration Register (CONFIG) COPD — COP Disable Bit COPD disables the COP module. See Chapter 6 Computer Operating Properly (COP) Module. 1 = COP module disabled 0 = COP module enabled MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Chapter 6 Computer Operating Properly (COP) Module 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register. 6.2 Functional Description Figure 6-1 shows the structure of the COP module.
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Computer Operating Properly (COP) Module The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 – 24 or 213 – 24 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 213 – 24 CGMXCLK cycle overflow option, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms.
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COP Control Register 6.3.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 6.3.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Chapter 5 Configuration Register (CONFIG). 6.3.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register.
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Computer Operating Properly (COP) Module 6.7.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction.
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Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.
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Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
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CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
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Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6.
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Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
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Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set.
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Instruction Set Summary Effect on CCR V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Description Operand Operation Opcode Source Form Address Mode Table
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Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Divide DIR INH INH 0 – – 0 1 – INH IX1 IX SP1 3F dd 4F 5F 8C 6F ff 7F 9E6F ff
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Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
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Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
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Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
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MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
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Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 8.2 Features Features of the IRQ module include: • A dedicated external interrupt pin (IRQ) • IRQ interrupt control bits • Hysteresis buffer • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Internal pullup resistor 8.
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External Interrupt (IRQ) RESET INTERNAL ADDRESS BUS ACK TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D CLR Q IRQ INTERRUPT REQUEST SYNCHRONIZER CK IRQ IMASK MODE TO MODE SELECT LOGIC HIGH VOLTAGE DETECT Figure 8-1.
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IRQ Pin 8.4 IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
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External Interrupt (IRQ) 8.6 IRQ Status and Control Register The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin Address: $001D Bit 7 6 5 4 Read: 3 2 IRQF 0 Write: Reset: ACK 0 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 = Unimplemented Figure 8-3.
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Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup device is also enabled on the pin. 9.
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Keyboard Interrupt Module (KBI) INTERNAL BUS CLOCK GENERATOR MODULE 1–8 MHz OSCILLATOR PHASE LOCKED LOOP 2-CHANNEL TIMER INTERFACE MODULE 1 VDDAD/VREFH VDDAD/VREFL SYSTEM INTEGRATION MODULE DDRA ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA PTE5–PTE2 PTE1/RxD PTE0/TxD 2-CHANNEL TIMER INTERFACE MODULE 2 COMPUTER OPERATING PROPERLY M
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Functional Description INTERNAL BUS VECTOR FETCH DECODER ACKK RESET KBD0 VDD . TO PULLUP ENABLE KEYF D CLR Q SYNCHRONIZER . CK KB0IE . KEYBOARD INTERRUPT REQUEST IMASKK KBD7 MODEK TO PULLUP ENABLE KB7IE Figure 9-2. Keyboard Module Block Diagram Addr. $001A $001B Register Name Keyboard Status Read: and Control Register Write: (INTKBSCR) See page 107. Reset: Keyboard Interrupt Enable Read: Register (INTKBIER) Write: See page 108.
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Keyboard Interrupt Module (KBI) The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0.
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Keyboard Module During Break Interrupts 9.5.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 9.6 Keyboard Module During Break Interrupts The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state.
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Keyboard Interrupt Module (KBI) ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK — Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit.
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Chapter 10 Low-Power Modes 10.1 Introduction The microcontroller (MCU) may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in the low-power modes. 10.1.1 Wait Mode The WAIT instruction puts the MCU in a low-power standby mode in which the central processor unit (CPU) clock is disabled but the bus clock continues to run.
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Low-Power Modes 10.3 Break Module (BRK) 10.3.1 Wait Mode If enabled, the break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set. 10.3.2 Stop Mode The break module is inactive in stop mode. The STOP instruction does not affect break module register states. 10.4 Central Processor Unit (CPU) 10.4.
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Computer Operating Properly Module (COP) 10.6 Computer Operating Properly Module (COP) 10.6.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. 10.6.2 Stop Mode Stop mode turns off the COPCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the CONFIG1 register enables the STOP instruction.
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Low-Power Modes 10.9 Low-Voltage Inhibit Module (LVI) 10.9.1 Wait Mode If enabled, the low-voltage inhibit (LVI) module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 10.9.2 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 10.10 Enhanced Serial Communications Interface Module (ESCI) 10.10.
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Timer Interface Module (TIM1 and TIM2) 10.12 Timer Interface Module (TIM1 and TIM2) 10.12.1 Wait Mode The timer interface modules (TIM) remain active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 10.12.2 Stop Mode The TIM is inactive in stop mode.
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Low-Power Modes 10.15 Exiting Wait Mode These events restart the CPU clock and load the program counter with the reset vector or with an interrupt vector: • External reset — A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. • External interrupt — A high-to-low transition on an external interrupt pin (IRQ pin) loads the program counter with the contents of locations: $FFFA and $FFFB; IRQ pin.
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Exiting Stop Mode 10.16 Exiting Stop Mode These events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: • External reset — A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF.
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Low-Power Modes MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF. 11.2 Features Features of the LVI module include: • Programmable LVI reset • Selectable LVI trip voltage • Programmable stop mode operation 11.3 Functional Description Figure 11-1 shows the structure of the LVI module. The LVI is enabled out of reset.
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Low-Voltage Inhibit (LVI) LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See Figure 5-2. Configuration Register 1 (CONFIG1) for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 16.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI.
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LVI Status Register 11.3.3 Voltage Hysteresis Protection Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS. 11.3.
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Low-Voltage Inhibit (LVI) 11.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 11.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 11.6.2 Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
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Chapter 12 MSCAN08 Controller (MSCAN08) 12.1 Introduction The MSCAN08 is the specific implementation of the MSCAN concept targeted for the M68HC08 Microcontroller Family. The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification dated September, 1991.
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MSCAN08 Controller (MSCAN08) INTERNAL BUS 1–8 MHz OSCILLATOR VDDAD/VREFH VDDAD/VREFL PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE PTE5–PTE2 PTE1/RxD PTE0/TxD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) 2-CHANNEL TIMER INTERFAC
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Message Storage CAN STATION 1 CAN NODE 1 CAN NODE 2 CAN NODE N MCU CAN CONTROLLER (MSCAN08) CANRX CANTX TRANSCEIVER CAN_H CAN_L CAN BUS Figure 12-2. The CAN System Each CAN station is connected physically to the CAN bus lines through a transceiver chip. The transceiver is capable of driving the large current needed for the CAN and has current protection against defected CAN or defected stations. 12.
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MSCAN08 Controller (MSCAN08) A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message being sent and as such reduces the reactiveness requirements on the CPU. Problems may arise if the sending of a message would be finished just while the CPU re-loads the second buffer. In that case, no buffer would then be ready for transmission and the bus would be released.
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Message Storage CPU08 I BUS MSCAN08 RxBG RxFG RXF Tx0 TXE PRIO Tx1 TXE PRIO Tx2 TXE PRIO Figure 12-3. User Model for Message Buffer Organization 12.4.3 Transmit Structures The MSCAN08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. The three buffers are arranged as shown in Figure 12-3. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see 12.
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MSCAN08 Controller (MSCAN08) To transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (TXE) flag in the MSCAN08 transmitter flag register (CTFLG) (see 12.13.7 MSCAN08 Transmitter Flag Register). The CPU08 then stores the identifier, the control bits and the data content into one of the transmit buffers. Finally, the buffer has to be flagged ready for transmission by clearing the TXE flag.
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Identifier Acceptance Filter 2. Two identifier acceptance filters, each to be applied to: a. The 14 most significant bits of the extended identifier plus the SRR and the IDE bits of CAN2.0B messages, or b. The 11 bits of the identifier plus the RTR and IDE bits of CAN 2.0A/B messages. Figure 12-5 shows how the 32-bit filter bank (CIDAR0–CIDAR3 and CIDMR0–CIDMR3) produces filter 0 and 1 hits. 3. Four identifier acceptance filters, each to be applied to the first eight bits of the identifier.
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MSCAN08 Controller (MSCAN08) ID28 IDR0 ID21 ID20 IDR1 ID10 IDR0 ID3 ID2 IDR1 AM7 CIDMR0 AM0 AC7 CIDAR0 AC0 ID15 ID14 IDE ID10 IDR2 ID7 ID6 IDR3 RTR IDR2 ID3 ID10 IDR3 ID3 ID ACCEPTED (FILTER 0 HIT) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID ACCEPTED (FILTER 1 HIT) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID ACCEPTED (FILTER 2 HIT) AM7 CIDMR3 AM0 AC7 CIDAR3 AC0 ID ACCEPTED (FILTER 3 HIT) Figure 12-6.
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Interrupts 12.6 Interrupts The MSCAN08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked. For details, see 12.13.5 MSCAN08 Receiver Flag Register (CRFLG) through 12.13.8 MSCAN08 Transmitter Control Register. 1. Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXE flags of the empty message buffers are set. 2.
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MSCAN08 Controller (MSCAN08) Table 12-1. MSCAN08 Interrupt Vector Addresses Function Source Local Mask Wakeup WUPIF WUPIE RWRNIF RWRNIE TWRNIF TWRNIE RERRIF RERRIE TERRIF TERRIE BOFFIF BOFFIE OVRIF OVRIE Error interrupts Receive Transmit RXF RXFIE TXE0 TXEIE0 TXE1 TXEIE1 TXE2 TXEIE2 Global Mask I bit 12.7 Protocol Violation Protection The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming errors.
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Low-Power Modes . Table 12-2. MSCAN08 versus CPU Operating Modes MSCAN08 Mode Power Down CPU Mode STOP WAIT or RUN (1) SLPAK = X SFTRES = X Sleep SLPAK = 1 SFTRES = 0 Soft Reset SLPAK = 0 SFTRES = 1 Normal SLPAK = 0 SFTRES = 0 1. ‘X’ means don’t care. 12.8.1 MSCAN08 Sleep Mode The CPU can request the MSCAN08 to enter the low-power mode by asserting the SLPRQ bit in the module configuration register (see Figure 12-7).
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MSCAN08 Controller (MSCAN08) MSCAN08 RUNNING MCU or MSCAN08 SLPRQ = 0 SLPAK = 0 MCU MSCAN08 SLEEPING SLEEP REQUEST SLPRQ = 1 SLPAK = 1 SLPRQ = 1 SLPAK = 0 MSCAN08 Figure 12-7. Sleep Request/Acknowledge Cycle After wakeup, the MSCAN08 waits for 11 consecutive recessive bits to synchronize to the bus. As a consequence, if the MSCAN08 is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered.
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Timer Link To protect the CAN bus system from fatal consequences resulting from violations of the above rule, the MSCAN08 drives the CANTX pin into recessive state. In power-down mode, no registers can be accessed. MSCAN08 bus activity can wake the MCU from CPU stop/MSCAN08 power-down mode. However, until the oscillator starts up and synchronization is achieved the MSCAN08 will not respond to incoming data. 12.8.4 CPU Wait Mode The MSCAN08 module remains active during CPU wait mode.
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MSCAN08 Controller (MSCAN08) CGMXCLK ÷2 OSC CGMOUT (TO SIM) BCS PLL ÷2 CGM MSCAN08 (2 * BUS FREQUENCY) ÷2 MSCANCLK PRESCALER (1 ... 64) CLKSRC Figure 12-8. Clocking Scheme NOTE If the system clock is generated from a PLL, it is recommended to select the crystal clock source rather than the system clock source due to jitter considerations, especially at faster CAN bus rates. A programmable prescaler is used to generate out of the MSCAN08 clock the time quanta (Tq) clock.
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Clock System The synchronization jump width (SJW) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The above parameters can be set by programming the bus timing registers, CBTR0 and CBTR1. See 12.13.3 MSCAN08 Bus Timing Register 0 and 12.13.4 MSCAN08 Bus Timing Register 1.
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MSCAN08 Controller (MSCAN08) 12.11 Memory Map The MSCAN08 occupies 128 bytes in the CPU08 memory space. The absolute mapping is implementation dependent with the base address being a multiple of 128. $0500 $0508 $0509 $050D $050E $050F $0510 $0517 $0518 $053F CONTROL REGISTERS 9 BYTES RESERVED 5 BYTES ERROR COUNTERS 2 BYTES IDENTIFIER FILTER 8 BYTES RESERVED 40 BYTES $0540 RECEIVE BUFFER $054F $0550 TRANSMIT BUFFER 0 $055F $0560 TRANSMIT BUFFER 1 $056F $0570 TRANSMIT BUFFER 2 $057F Figure 12-10.
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Programmer’s Model of Message Storage 12.12 Programmer’s Model of Message Storage This section details the organization of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers.
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MSCAN08 Controller (MSCAN08) Addr.
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Programmer’s Model of Message Storage Addr. Register $05b0 IDR0 $05b1 IDR1 $05b2 IDR2 $05b3 IDR3 Read: Write: Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE (=0) Read: Write: Read: Write: = Unimplemented Figure 12-13. Standard Identifier Mapping 12.12.2 Identifier Registers The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29 bits (ID28–ID0) for the extended format.
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MSCAN08 Controller (MSCAN08) 12.12.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. DLC3–DLC0 — Data Length Code Bits The data length code contains the number of bytes (data byte count) of the respective message. At transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 12-5 shows the effect of setting the DLC bits. Table 12-5.
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Programmer’s Model of Control Registers 12.13 Programmer’s Model of Control Registers The programmer’s model has been laid out for maximum simplicity and efficiency. Figure 12-15 gives an overview on the control register block of the MSCAN08. Addr.
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MSCAN08 Controller (MSCAN08) Addr.
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Programmer’s Model of Control Registers SLPAK — Sleep Mode Acknowledge This flag indicates whether the MSCAN08 is in module internal sleep mode. It shall be used as a handshake for the sleep mode request (see 12.8.1 MSCAN08 Sleep Mode). If the MSCAN08 detects bus activity while in sleep mode, it clears the flag.
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MSCAN08 Controller (MSCAN08) WUPM — Wakeup Mode This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from spurious wakeups (see 12.8.5 Programmable Wakeup Function). 1 = MSCAN08 will wakeup the CPU only in cases of a dominant pulse on the bus which has a length of at least twup. 0 = MSCAN08 will wakeup the CPU after any recessive-to-dominant edge on the CAN bus. CLKSRC — Clock Source This flag defines which clock source the MSCAN08 module is driven from (see 12.
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Programmer’s Model of Control Registers Table 12-7. Baud Rate Prescaler BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler Value (P) 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : : : : : : : : 1 1 1 1 1 1 64 NOTE The CBTR0 register can be written only if the SFTRES bit in the MSCAN08 module control register is set. 12.13.
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MSCAN08 Controller (MSCAN08) Table 12-8. Time Segment Values TSEG13 TSEG12 TSEG11 TSEG10 Time Segment 1 TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 0 1 Tq Cycle(1) 0 0 0 1 Tq Cycle(1) 0 0 0 1 2 Tq Cycles(1) 0 0 1 2 Tq Cycles 0 0 1 0 3Tq Cycles(1) . . . . 0 0 1 1 4 Tq Cycles . . . . . . . . . 1 1 1 8Tq Cycles . . . . . 1 1 1 1 16 Tq Cycles 1. This setting is not valid. Please refer to Table 12-4 for valid settings. 12.13.
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Programmer’s Model of Control Registers TWRNIF — Transmitter Warning Interrupt Flag This flag is set when the MSCAN08 goes into warning status due to the transmit error counter (TEC) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set(1). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into transmitter warning status. 0 = No transmitter warning status has been reached.
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MSCAN08 Controller (MSCAN08) The CRFLG register is held in the reset state when the SFTRES bit in CMCR0 is set. 12.13.6 MSCAN08 Receiver Interrupt Enable Register Address: Read: Write: Reset: $0505 Bit 7 6 5 4 3 2 1 Bit 0 WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE 0 0 0 0 0 0 0 0 Figure 12-21. Receiver Interrupt Enable Register (CRIER) WUPIE — Wakeup Interrupt Enable 1 = A wakeup event will result in a wakeup interrupt. 0 = No interrupt will be generated from this event.
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Programmer’s Model of Control Registers 12.13.7 MSCAN08 Transmitter Flag Register The abort acknowledge flags are read only. The transmitter buffer empty flags are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting. The transmitter buffer empty flags each have an associated interrupt enable bit in the CTCR register. A hard or soft reset will resets the register.
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MSCAN08 Controller (MSCAN08) 12.13.8 MSCAN08 Transmitter Control Register Address: $0507 Bit 7 Read: 0 Write: Reset: 0 6 5 4 ABTRQ2 ABTRQ1 ABTRQ0 0 0 0 3 0 2 1 Bit 0 TXEIE2 TXEIE1 TXEIE0 0 0 0 0 = Unimplemented Figure 12-23. Transmitter Control Register (CTCR) ABTRQ2–ABTRQ0 — Abort Request The CPU sets an ABTRQx bit to request that an already scheduled message buffer (TXE = 0) be aborted.
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Programmer’s Model of Control Registers IDAM1–IDAM0— Identifier Acceptance Mode The CPU sets these flags to define the identifier acceptance filter organization (see 12.5 Identifier Acceptance Filter). Table 12-9 summarizes the different settings. In “filter closed” mode no messages will be accepted so that the foreground buffer will never be reloaded. Table 12-9.
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MSCAN08 Controller (MSCAN08) 12.13.11 MSCAN08 Transmit Error Counter Address: Read: $050F Bit 7 6 5 4 3 2 1 Bit 0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0 0 0 0 0 0 0 Write: Reset: 0 = Unimplemented Figure 12-26. Transmit Error Counter (CTXERR) This read-only register reflects the status of the MSCAN08 transmit error counter. NOTE Both error counters may only be read when in sleep or soft reset mode. 12.13.
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Programmer’s Model of Control Registers AC7–AC0 — Acceptance Code Bits AC7–AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. NOTE The CIDAR0–CIDAR3 registers can be written only if the SFTRES bit in CMCR0 is set 12.13.
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MSCAN08 Controller (MSCAN08) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Chapter 13 Input/Output (I/O) Ports 13.1 Introduction Bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with pullup devices if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode. 13.
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Input/Output (I/O) Ports Addr. $0004 $0005 $0006 $0007 $0008 $000C $000D $000E $000F Register Name Bit 7 6 5 4 3 2 1 Bit 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Read: Port E Data Register (PTE) Write: See page 167.
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Unused Pin Termination Table 13-1.
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Input/Output (I/O) Ports 13.3 Port A Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module. Port A also has software configurable pullup devices if configured as an input port. 13.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins.
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Port A Figure 13-4 shows the port A I/O logic. READ DDRA ($0004) WRITE DDRA ($0004) DDRAx INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx VDD PTAPUEx INTERNAL PULLUP DEVICE READ PTA ($0000) Figure 13-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
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Input/Output (I/O) Ports PTAPUE7–PTAPUE0 — Port A Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected 13.4 Port B Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (ADC) module. 13.4.
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Port B Address: Read: Write: Reset: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 13-7. Data Direction Register B (DDRB) DDRB7–DDRB0 — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB7–DDRB0, configuring all port B pins as inputs.
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Input/Output (I/O) Ports 13.5 Port C Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. 13.5.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the seven port C pins. NOTE Bit 6 through bit 2 of PTC are not available in the 32-pin LQFP package.
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Port C DDRC6–DDRC0 — Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC6–DDRC0, configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 13-11 shows the port C I/O logic.
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Input/Output (I/O) Ports 13.5.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRC is configured for output mode.
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Port D T1CH1 and T1CH0 — Timer 1 Channel I/O Bits The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 19 Timer Interface Module (TIM). SPSCK — SPI Serial Clock The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the PTD3/SPSCK pin is available for general-purpose I/O.
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Input/Output (I/O) Ports READ DDRD ($0007) WRITE DDRD ($0007) DDRDx INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx VDD PTDPUEx INTERNAL PULLUP DEVICE READ PTD ($0003) Figure 13-15. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
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Port E PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port D pin configured to have internal pullup 0 = Corresponding port D pin has internal pullup disconnected 13.7 Port E Port E is a 6-bit special-function port that shares two of its pins with the enhanced serial communications interface (ESCI) module. 13.7.
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Input/Output (I/O) Ports Address: Read: $000C Bit 7 6 0 0 Write: Reset: 0 5 4 3 2 1 Bit 0 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0 0 = Unimplemented Figure 13-18. Data Direction Register E (DDRE) DDRE5–DDRE0 — Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE5–DDRE0, configuring all port E pins as inputs.
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Chapter 14 Resets and Interrupts 14.1 Introduction Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the microcontroller (MCU) to its startup condition. An interrupt vectors the program counter to a service routine. 14.2 Resets A reset immediately returns the MCU to a known startup condition and begins program execution from a user-defined memory location. 14.2.
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Resets and Interrupts 14.2.3.1 Power-On Reset (POR) A power-on reset (POR) is an internal reset caused by a positive transition on the VDD pin. VDD at the POR must go below VPOR to reset the MCU. This distinguishes between a reset and a POR. The POR is not a brown-out detector, low-voltage detector, or glitch detector.
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Resets 14.2.3.4 Illegal Opcode Reset An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal opcode reset sets the ILOP bit in the SIM reset status register. If the stop enable bit, STOP, in the mask option register is a logic 0, the STOP instruction causes an illegal opcode reset. 14.2.3.5 Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped address.
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Resets and Interrupts ILAD — Illegal Address Reset Bit 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR since any reset MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by forced monitor mode entry. 0 = POR or read of SRSR since any reset LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by low-power supply voltage 0 = POR or read of SRSR since any reset 14.
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Interrupts After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the example shown in Figure 14-4, if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
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Resets and Interrupts FROM RESET BREAK INTERRUPT ? NO YES YES BITSET? SET? IIBIT NO IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO YES OTHER INTERRUPTS ? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION ? YES NO RTI INSTRUCTION ? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 14-5. Interrupt Processing MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Interrupts Table 14-1.
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Resets and Interrupts 14.3.2.3 IRQ Pin A logic 0 on the IRQ1 pin latches an external interrupt request. 14.3.2.4 Clock Generator (CGM) The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or leaves the locked state. When the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the PLL bandwidth control register. PLLF is in the PLL control register. 14.3.2.
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Interrupts • Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE, enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control register. 14.3.2.
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Resets and Interrupts 14.3.2.11 Timebase Module (TBM) The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing a logic 1 to the TACK bit. 14.3.2.
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Interrupts • Bus Off bit (BOFFIF) — BOFFIF is set when the transmit error counter has exceeded 255 and MSCAN08 has gone to bus off state. The bus off interrupt enable bit, BOFFIE, enables BOFFIF to generate MSCAN08 error CPU interrupt requests. BOFFIF is in MSCAN08 receiver flag register. BOFFIE is in MSCAN08 receiver interrupt enable register. 14.3.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources.
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Resets and Interrupts 14.3.3.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 14-6. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Table 14-2. 1 = Interrupt request present 0 = No interrupt request present Bit 1 and Bit 0 — Always read 0 14.3.3.
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Chapter 15 Enhanced Serial Communications Interface (ESCI) Module 15.1 Introduction The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU). 15.
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Enhanced Serial Communications Interface (ESCI) Module INTERNAL BUS 1–8 MHz OSCILLATOR VDDAD/VREFH VDDAD/VREFL PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE PTE5–PTE2 PTE1/RxD PTE0/TxD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1)
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Pin Name Conventions 15.3 Pin Name Conventions The generic names of the ESCI input/output (I/O) pins are: • RxD (receive data) • TxD (transmit data) ESCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an ESCI input or output reflects the name of the shared port pin. Table 15-1 shows the full names and the generic names of the ESCI I/O pins. The generic pin names appear in the text of this section. Table 15-1.
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Enhanced Serial Communications Interface (ESCI) Module INTERNAL BUS ERROR INTERRUPT CONTROL RxD SCI_TxD TxD TRANSMIT SHIFT REGISTER TXINV LINR SCTIE BUS_CLK R8 TCIE SL T8 SCRIE ILIE TE ACLK BIT IN SCIACTL SCTE RE ARBITER RECEIVE SHIFT REGISTER RxD ESCI DATA REGISTER RECEIVER INTERRUPT CONTROL TRANSMITTER INTERRUPT CONTROL ESCI DATA REGISTER SBK SCRF OR ORIE IDLE NF NEIE FE FEIE PE SCI_CLK TC RWU PEIE LOOPS LOOPS WAKEUP CONTROL BUS CLOCK RECEIVE CONTROL ENSCI ENHANCED PRE
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Functional Description Addr. $0009 $000A $000B $0013 $0014 $0015 $0016 $0017 $0018 $0019 Register Name Read: ESCI Prescaler Register (SCPSC) Write: See page 206. Reset: Read: ESCI Arbiter Control Register (SCIACTL) Write: See page 209. Reset: Read: ESCI Arbiter Data Register (SCIADAT) Write: See page 210. Reset: Read: ESCI Control Register 1 (SCC1) Write: See page 196. Reset: Read: ESCI Control Register 2 (SCC2) Write: See page 198.
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Enhanced Serial Communications Interface (ESCI) Module 15.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 15-4. PARITY OR DATA BIT 8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 STOP BIT PARITY OR DATA BIT 9-BIT DATA FORMAT (BIT M IN SCC1 SET) START BIT NEXT START BIT BIT 6 BIT 7 BIT 8 NEXT START BIT STOP BIT Figure 15-4.
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Functional Description 15.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). 15.4.2.2 Character Transmission During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin.
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Enhanced Serial Communications Interface (ESCI) Module Receiving a break character has these effects on ESCI registers: • Sets the framing error bit (FE) in SCS1 • Sets the ESCI receiver full bit (SCRF) in SCS1 • Clears the ESCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits 15.4.2.
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Functional Description 15.4.3 Receiver Figure 15-6 shows the structure of the ESCI receiver. The receiver I/O registers are summarized in Figure 15-3.
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Enhanced Serial Communications Interface (ESCI) Module 15.4.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 15.4.3.2 Character Reception During an ESCI reception, the receive shift register shifts characters in from the RxD pin.
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Functional Description Table 15-2. Start Bit Verification (Continued) RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 15-3 summarizes the results of the data bit samples. Table 15-3.
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Enhanced Serial Communications Interface (ESCI) Module 15.4.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. 15.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate.
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Functional Description The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: 170 – 163 -------------------------- × 100 = 4.12% 170 Fast Data Tolerance Figure 15-9 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10.
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Enhanced Serial Communications Interface (ESCI) Module Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: 1. Address mark — An address mark is a logic 1 in the MSB position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the ESCI receiver full bit, SCRF.
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Low-Power Modes 15.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 15.5.1 Wait Mode The ESCI module remains active in wait mode. Any enabled CPU interrupt request from the ESCI module can bring the MCU out of wait mode. If ESCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. 15.5.2 Stop Mode The ESCI module is inactive in stop mode.
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Enhanced Serial Communications Interface (ESCI) Module 15.8 I/O Registers These I/O registers control and monitor ESCI operation: • ESCI control register 1, SCC1 • ESCI control register 2, SCC2 • ESCI control register 3, SCC3 • ESCI status register 1, SCS1 • ESCI status register 2, SCS2 • ESCI data register, SCDR • ESCI baud rate register, SCBR • ESCI prescaler register, SCPSC • ESCI arbiter control register, SCIACTL • ESCI arbiter data register, SCIADAT 15.8.
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I/O Registers TXINV — Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE Setting the TXINV bit inverts all transmitted values including idle, break, start, and stop bits. M — Mode (Character Length) Bit This read/write bit determines whether ESCI characters are eight or nine bits long (See Table 15-5).The ninth bit can serve as a receiver wakeup signal or as a parity bit.
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Enhanced Serial Communications Interface (ESCI) Module PTY — Parity Bit This read/write bit determines whether the ESCI generates and checks for odd parity or even parity (see Table 15-5). Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE Changing the PTY bit in the middle of a transmission or reception can generate a parity error. 15.8.
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I/O Registers ILIE — Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate ESCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin.
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Enhanced Serial Communications Interface (ESCI) Module 15.8.3 ESCI Control Register 3 ESCI control register 3 (SCC3): • Stores the ninth ESCI data bit received and the ninth ESCI data bit to be transmitted. • Enables these interrupts: – Receiver overrun – Noise error – Framing error – Parity error Address: $0015 Bit 7 Read: R8 Write: Reset: U 6 5 4 3 2 1 Bit 0 T8 R R ORIE NEIE FEIE PEIE 0 0 0 0 0 = Unimplemented 0 0 R = Reserved U = Unaffected Figure 15-12.
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I/O Registers 15.8.4 ESCI Status Register 1 ESCI status register 1 (SCS1) contains flags to signal these conditions: • Transfer of SCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to SCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: Read: $0016 Bit 7 6 5 4 3 2 1 Bit 0 SCTE TC SCRF IDLE OR NF FE PE 1 0 0 0 0 0 0 Write: Reset: 1 = Unimplemented Figure 15-13.
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Enhanced Serial Communications Interface (ESCI) Module must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit.
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I/O Registers NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the ESCI detects noise on the RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit.
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Enhanced Serial Communications Interface (ESCI) Module 15.8.6 ESCI Data Register The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the ESCI data register. Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 15-16.
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I/O Registers Table 15-6. ESCI LIN Control Bits LINT LINR M Functionality 0 0 X Normal ESCI functionality 0 1 0 13-bit break detect enabled for LIN receiver 0 1 1 14-bit break detect enabled for LIN receiver 1 0 0 13-bit generation enabled for LIN transmitter 1 0 1 14-bit generation enabled for LIN transmitter 1 1 0 13-bit break detect/11-bit generation enabled for LIN 1 1 1 14-bit break detect/12-bit generation enabled for LIN In LIN (version 1.
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Enhanced Serial Communications Interface (ESCI) Module 15.8.8 ESCI Prescaler Register The ESCI prescaler register (SCPSC) together with the ESCI baud rate register selects the baud rate for both the receiver and the transmitter. NOTE There are two prescalers available to adjust the baud rate. One in the ESCI baud rate register and one in the ESCI prescaler register.
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I/O Registers Table 15-11 shows the ESCI baud rates that can be generated with a 4.9152-MHz bus frequency. Table 15-10. ESCI Prescaler Divisor Fine Adjust PSSB[4:3:2:1:0] Prescaler Divisor Fine Adjust (PDFA) 0 0 0 0 0 0/32 = 0 0 0 0 0 1 1/32 = 0.03125 0 0 0 1 0 2/32 = 0.0625 0 0 0 1 1 3/32 = 0.09375 0 0 1 0 0 4/32 = 0.125 0 0 1 0 1 5/32 = 0.15625 0 0 1 1 0 6/32 = 0.1875 0 0 1 1 1 7/32 = 0.21875 0 1 0 0 0 8/32 = 0.25 0 1 0 0 1 9/32 = 0.28125 0 1 0 1 0 10/32 = 0.
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Enhanced Serial Communications Interface (ESCI) Module Table 15-11. ESCI Baud Rate Selection Examples PS[2:1:0] PSSB[4:3:2:1:0] SCP[1:0] Prescaler Divisor (BPD) SCR[2:1:0] Baud Rate Divisor (BD) 0 0 0 X X X X X 0 0 1 0 0 0 1 76,800 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 9600 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 9562.65 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 9525.58 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 8563.
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ESCI Arbiter 15.9 ESCI Arbiter The ESCI module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time detection. The arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. The CPU can control operation mode via the ESCI arbiter control register (SCIACTL). 15.9.
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Enhanced Serial Communications Interface (ESCI) Module ARUN— Arbiter Counter Running Flag This read-only bit indicates the arbiter counter is running. Reset clears ARUN. 1 = Arbiter counter running 0 = Arbiter counter stopped AROVFL— Arbiter Counter Overflow Bit This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to SCIACTL. Writing logic 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears AROVFL.
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Freescale Semiconductor CPU READS RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 COUNTER STARTS, ARUN = 1 CPU WRITES SCIACTL WITH $30 CPU READS RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 CPU WRITES SCIACTL WITH $30 COUNTER STARTS, ARUN = 1 CPU READS RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 COUNTER STARTS, ARUN = 1 CPU WRITES SCIACTL WITH $20 ESCI Arbiter MEASURED TIME RXD Figure 15-21. Bit Time Measurement with ACLK = 0 MEASURED TIME RXD Figure 15-22.
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Enhanced Serial Communications Interface (ESCI) Module 15.9.4 Arbitration Mode If AM[1:0] is set to 10, the arbiter module operates in arbitration mode. On every rising edge of SCI_TxD (output of the ESCI module, internal chip signal), the counter is started. When the counter reaches $38 (ACLK = 0) or $08 (ACLK = 1), RxD is statically sensed. If in this case, RxD is sensed low (for example, another bus is driving the bus dominant) ALOST is set.
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Chapter 16 System Integration Module (SIM) 16.1 Introduction This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 16-1. Table 16-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing.
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System Integration Module (SIM) The SIM is responsible for: • Bus clock generation and control for CPU and peripherals: – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout • Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources Table 16-1 shows the internal signal
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SIM Bus Clock Control and Generation 16.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 16-3. This clock originates from either an external oscillator or from the on-chip PLL. 16.2.
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System Integration Module (SIM) 16.3 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address • Forced monitor mode entry reset (MODRST) All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST).
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Reset and System Initialization 16.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset continues to be asserted for an additional 32 cycles at which point the reset vector will be fetched. See Figure 16-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 16-6.
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System Integration Module (SIM) 16.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor mode.
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SIM Counter 16.3.2.6 Monitor Mode Entry Module Reset (MODRST) The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are erased ($FF) (see 20.3.1.1 Normal Monitor Mode). When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources. 16.
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System Integration Module (SIM) Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See Figure 16-10.
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Exception Control FROM RESET BREAK I BIT SET? INTERRUPT? YES NO YES I BIT SET? NO IRQ INTERRUPT? YES NO AS MANY INTERRUPTS AS EXIST ON CHIP STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 16-10. Interrupt Processing MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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System Integration Module (SIM) 16.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts.
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Exception Control 16.5.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 16.5.1.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources.
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System Integration Module (SIM) Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: I6 I5 I4 I3 I2 I1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 16-12. Interrupt Status Register 1 (INT1) I6–I1 — Interrupt Flags 1–6 These flags indicate the presence of interrupt requests from the sources shown in Table 16-3.
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Low-Power Modes 16.5.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 16.5.3 Break Interrupts The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output (see Chapter 19 Timer Interface Module (TIM)). The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 16.5.
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System Integration Module (SIM) IAB WAIT ADDR IDB WAIT ADDR + 1 PREVIOUS DATA SAME SAME NEXT OPCODE SAME SAME R/W Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 16-15. Wait Mode Entry Timing Figure 16-16 and Figure 16-17 show the timing for WAIT recovery. IAB $6E0B IDB $A6 $A6 $6E0C $A6 $00FF $01 $0B $00FE $00FD $00FC $6E EXITSTOPWAIT Note: EXITSTOPWAIT = RST pin or CPU interrupt Figure 16-16.
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SIM Registers NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit. The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 16-18 shows stop mode entry timing. Figure 16-19 shows stop mode recovery time from interrupt. NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
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System Integration Module (SIM) 16.7.1 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: Read: Write: Reset: $FE00 Bit 7 6 5 4 3 2 R R R R R R 0 0 0 0 0 0 R = Reserved 1 SBSW Note(1) 0 Bit 0 R 0 1. Writing a logic 0 clears SBSW. Figure 16-20. Break Status Register (BSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine.
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SIM Registers ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = VDD 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR 16.7.
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System Integration Module (SIM) MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Chapter 17 Serial Peripheral Interface (SPI) Module 17.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 17.
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Serial Peripheral Interface (SPI) Module INTERNAL BUS 1–8 MHz OSCILLATOR VDDAD/VREFH VDDAD/VREFL PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE PTE5–PTE2 PTE1/RxD PTE0/TxD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) 2-CHANNEL TI
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Functional Description 17.4 Functional Description Figure 17-2 summarizes the SPI I/O registers and Figure 17-3 shows the structure of the SPI module. The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt driven. If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. See 13.5.
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Serial Peripheral Interface (SPI) Module INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT ÷ 2 FROM SIM SHIFT REGISTER 7 6 5 4 3 2 1 MISO 0 ÷2 CLOCK DIVIDER MOSI ÷8 RECEIVE DATA REGISTER ÷ 32 PIN CONTROL LOGIC ÷ 128 SPMSTR CLOCK SELECT SPE SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR RESERVED TRANSMITTER CPU INTERRUPT REQUEST RESERVED CPHA MODFEN CPOL SPWOM ERRIE SPI CONTROL SPTIE SPRIE RECEIVER/ERROR CPU INTERRUPT REQUEST SPE SPRF SPTE OVRF MODF Figure 17-3.
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Transmission Formats 17.4.2 Slave Mode The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0. SS must remain low until the transmission is complete. See 17.7.2 Mode Fault Error. In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module.
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Serial Peripheral Interface (SPI) Module 17.5.2 Transmission Format When CPHA = 0 Figure 17-5 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1.
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Transmission Formats 17.5.3 Transmission Format When CPHA = 1 Figure 17-7 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
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Serial Peripheral Interface (SPI) Module WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 6 BIT 5 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 1 2 3 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR LATEST SPSCK = INTERNAL CLOCK ÷ 2; 2 POSSIBLE START POINTS BUS CLOCK EARLIEST WRITE TO SPDR SPSCK = INTERNAL CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 32; 32 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷
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Queuing Transmission Data 17.6 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high.
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Serial Peripheral Interface (SPI) Module 17.7 Error Conditions The following flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register.
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Error Conditions In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 17-11 illustrates this process.
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Serial Peripheral Interface (SPI) Module MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 17-12.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set.
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Interrupts 17.8 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests. See Table 17-2. Table 17-2.
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Serial Peripheral Interface (SPI) Module The following sources in the SPI status and control register can generate CPU interrupt requests: • SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request.
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SPI During Break Interrupts 17.11 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See Chapter 16 System Integration Module (SIM). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit.
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Serial Peripheral Interface (SPI) Module 17.12.2 MOSI (Master Out/Slave In) MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. 17.12.
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I/O Registers The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register. See Table 17-3. Table 17-3. SPI Configuration SPE SPMSTR MODFEN SPI Configuration State of SS Logic 0 X(1)) X Not enabled General-purpose I/O; SS ignored by SPI 1 0 X Slave Input-only to SPI 1 1 0 Master without MODF General-purpose I/O; SS ignored by SPI 1 1 1 Master with MODF Input-only to SPI 1. X = Don’t care 17.12.
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Serial Peripheral Interface (SPI) Module SPMSTR — SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 17-5 and Figure 17-7.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit.
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I/O Registers Address: $0011 Bit 7 Read: SPRF Write: Reset: 0 6 ERRIE 0 5 4 3 OVRF MODF SPTE 0 0 1 2 1 Bit 0 MODFEN SPR1 SPR0 0 0 0 = Unimplemented Figure 17-15. SPI Status and Control Register (SPSCR) SPRF — SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
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Serial Peripheral Interface (SPI) Module MODFEN — Mode Fault Enable Bit This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a general-purpose I/O.
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Chapter 18 Timebase Module (TBM) 18.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external clock source. This TBM version uses 15 divider stages, eight of which are user selectable. A configuration option bit to select an additional 128 divide of the external clock source can be selected. See Chapter 5 Configuration Register (CONFIG) 18.
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Timebase Module (TBM) TBMCLKSEL FROM CONFIG2 CGMXCLK FROM CGM MODULE TBMCLK 0 1 DIVIDE BY 128 PRESCALER TBON ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 TACK ÷2 TBR0 ÷2 TBR1 ÷2 TBR2 TBMINT TBIF 000 TBIE R 001 010 100 SEL 011 101 110 111 Figure 18-1. Timebase Block Diagram 18.
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Low-Power Modes Table 18-1. Timebase Divider Selection Divider Tap TBR2 TBR1 TBR0 TMBCLKSEL 0 1 0 0 0 32,768 4,194,304 0 0 1 8192 1,048,576 0 1 0 2048 262144 0 1 1 128 16,384 1 0 0 64 8192 1 0 1 32 4096 1 1 0 16 2048 1 1 1 8 1024 As an example, a clock source of 4.9152 MHz, with the TMCLKSEL set for divide-by-128 and the TBR2–TBR0 set to {011}, the divider tap is1 and the interrupt rate calculates to: 1/(4.
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Timebase Module (TBM) 18.7 Timebase Control Register The timebase has one register, the timebase control register (TBCR), which is used to enable the timebase interrupts and set the rate. Address: $001C Bit 7 Read: TBIF Write: Reset: 0 6 5 4 TBR2 TBR1 TBR0 0 0 0 = Unimplemented 3 2 1 Bit 0 TBIE TBON R 0 0 0 0 R = Reserved 0 TACK Figure 18-2. Timebase Control Register (TBCR) TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over.
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Chapter 19 Timer Interface Module (TIM) 19.1 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 19-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
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Timer Interface Module (TIM) INTERNAL BUS 1–8 MHz OSCILLATOR VDDAD/VREFH VDDAD/VREFL PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE PTE5–PTE2 PTE1/RxD PTE0/TxD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) 2-CHANNEL TIMER INTERFAC
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Features 19.2 Features Features of the TIM include: • Two input capture/output compare channels: – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action • Buffered and unbuffered pulse-width-modulation (PWM) signal generation • Programmable TIM clock input with 7-frequency internal bus clock prescaler selection • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits 19.
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Timer Interface Module (TIM) Addr. Register Name Bit 7 6 5 TOIE TSTOP 4 3 0 0 2 1 Bit 0 PS2 PS1 PS0 Timer 1 Status and Control Read: Register (T1SC) Write: See page 265. Reset: TOF 0 0 1 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 $0021 Timer 1 Counter Read: Register High (T1CNTH) Write: See page 266. Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 $0022 Timer 1 Counter Read: Register Low (T1CNTL) Write: See page 266.
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Functional Description Addr. $002D $002E $002F Register Name Timer 2 Counter Read: Register Low (T2CNTL) Write: See page 266. Reset: Timer 2 Counter Modulo Read: Register High (T2MODH) Write: See page 267. Reset: Timer 2 Counter Modulo Read: Register Low (T2MODL) Write: See page 267. Reset: Timer 2 Channel 0 Status and Read: $0030 Control Register (T2SC0) Write: See page 267. Reset: $0031 $0032 Timer 2 Channel 0 Read: Register High (T2CH0H) Write: See page 270.
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Timer Interface Module (TIM) 19.4.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 19.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 19.4.
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Functional Description 19.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal.
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Timer Interface Module (TIM) Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.
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Interrupts 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 19-3. b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 19-3.
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Timer Interface Module (TIM) If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 19.6.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. 19.7 TIM During Break Interrupts A break interrupt stops the TIM counter.
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I/O Registers 19.9.1 TIM Status and Control Register The TIM status and control register (TSC): • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock Address: T1SC, $0020 and T2SC, $002B Read: Write: Reset: Bit 7 TOF 0 0 6 5 TOIE TSTOP 0 1 = Unimplemented 4 0 TRST 0 3 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 Figure 19-5.
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Timer Interface Module (TIM) PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 19-2 shows. Reset clears the PS[2:0] bits. Table 19-2.
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I/O Registers 19.9.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
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Timer Interface Module (TIM) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF.
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I/O Registers Table 19-3.
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Timer Interface Module (TIM) 19.9.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read.
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Chapter 20 Development Support 20.1 Introduction This section describes the break module, the monitor read-only memory (MON), and the monitor mode entry methods. 20.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
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Development Support ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] BKPT (TO SIM) CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] Figure 20-1. Break Module Block Diagram Addr. Register Name $FE00 Read: Break Status Register (BSR) Write: See page 275.
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Break Module (BRK) When the internal address bus matches the value written in the break address registers or when software writes a logic 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not ex
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Development Support 20.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0B Read: Write: Reset: Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 20-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7.
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Monitor ROM (MON) 20.2.2.3 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: $FE00 Bit 7 Read: Write: 6 R R 5 R 4 R 3 R 2 R 1 SBSW Note(1) Reset: Bit 0 R 0 R = Reserved 1. Writing a logic 0 clears SBSW. Figure 20-6. Break Status Register (BSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine.
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Development Support computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
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Monitor ROM (MON) POR RESET NO CONDITIONS FROM Table 20-1 PTA0 = 1, PTA1 = 0, RESET VECTOR BLANK? IRQ = VTST? YES PTA0 = 1, PTA1 = 0, PTB0 = 1, AND PTB1 = 0? NO NO YES YES FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE INVALID USER MODE HOST SENDS 8 SECURITY BYTES IS RESET POR? YES NO YES ARE ALL SECURITY BYTES CORRECT? ENABLE FLASH NO DISABLE FLASH MONITOR MODE ENTRY DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) EXECUTE MONITOR CODE YES DOES RESET OCCUR? NO Fi
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Development Support MC68HC908GZ16 N.C. RST VDD 47 pF VDDA OSC2 MAX232 1 1 μF + 4 0.1 μF 1 μF + 10 k 1 kΩ IRQ 3 10 k 1 μF 74HC125 3 2 9 PTA1 10 kΩ 74HC125 5 6 10 8 10 k PTB1 9.1 V DB9 7 PTB0 VDD + 2 PTB4 V– 6 5 C2– 10 k 1 μF V+ 2 C2+ + VDD OSC1 8 MHz GND 15 C1– 10 MΩ 27 pF + 3 1 μF VDD VCC 16 C1+ VDD PTA0 VSSA VSS 4 1 5 Figure 20-9. Normal Monitor Mode Circuit MC68HC908GZ16 N.C. RST 47 pF OSC2 MAX232 1 1 μF + 4 GND 15 C2+ V+ 2 5 C2– 1 μF 1 μF + N.
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Freescale Semiconductor Table 20-1. Monitor Mode Signal Requirements and Options Mode — IRQ MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4 User MON08 Function [Pin No.
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Development Support Enter monitor mode with pin configuration shown in Table 20-1 by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes (see 20.3.2 Security). After the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command. 20.3.1.
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Monitor ROM (MON) Table 20-2. Mode Differences Functions Modes Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD 20.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
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Development Support The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE Wait one bit time after each echo before sending the next byte.
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Monitor ROM (MON) Table 20-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE ADDRESS HIGH WRITE ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 20-5.
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Development Support Table 20-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 20-8.
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Monitor ROM (MON) 20.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
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Development Support MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev.
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Chapter 21 Electrical Specifications 21.1 Introduction This section contains electrical and timing specifications. 21.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 21.5 5-Vdc Electrical Characteristics and 21.6 3.3-Vdc Electrical Characteristics for guaranteed operating conditions.
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Electrical Specifications 21.3 Functional Operating Range Characteristic Symbol Value Unit TA –40 to +125 °C VDD 5.0 ±10% 3.3 ±10% V Symbol Value Unit Thermal resistance 32-pin LQFP 48-pin LQFP θJA 95 95 °C/W I/O pin power dissipation PI/O User determined W Power dissipation(1) PD PD = (IDD × VDD) + PI/O = K/(TJ + 273 °C) W Constant(2) K Average junction temperature TJ Operating temperature range Operating voltage range 21.
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5-Vdc Electrical Characteristics 21.5 5-Vdc Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.8 VDD – 1.5 VDD – 1.5 — — — — — — — V V V — 50 mA IOH2 — — 50 mA IOHT — — 100 mA VOL VOL VOL IOL1 — — — — — — 0.4 1.5 1.5 V V V — — 50 mA IOL2 — — 50 mA IOLT — — 100 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.2 × VDD V — — — — — — 20 6 0.6 1 1.
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Electrical Specifications Symbol Min Typ(2) Max Unit VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 3.90 4.25 4.50 V Low-voltage inhibit, trip rising voltage VTRIPR 4.20 4.35 4.60 V Low-voltage inhibit reset/recover hysteresis (VTRIPF + VHYS = VTRIPR) VHYS — 100 — mV POR rearm voltage(12) VPOR 0 — 100 mV POR reset voltage(13) VPORRST 0 700 800 mV RPOR 0.
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3.3-Vdc Electrical Characteristics 21.6 3.3-Vdc Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.3 VDD – 1.0 VDD – 1.0 — — — — — — — V V V — 30 mA IOH2 — — 30 mA IOHT — — 60 mA VOL VOL VOL IOL1 — — — — — — 0.3 1.0 0.8 V V V — — 30 mA IOL2 — — 30 mA IOLT — — 60 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.3 × VDD V — — — — — — 8 3 0.
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Electrical Specifications Symbol Min Typ(2) Max Unit VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 2.35 2.6 2.7 V Low-voltage inhibit, trip rising voltage VTRIPR 2.4 2.66 2.8 V Low-voltage inhibit reset/recover hysteresis (VTRIPF + VHYS = VTRIPR) VHYS — 100 — mV POR rearm voltage(12) VPOR 0 — 100 mV POR reset voltage(13) VPORRST 0 700 800 mV RPOR 0.
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5.0-Volt Control Timing 21.7 5.0-Volt Control Timing Symbol Min Max Unit fOSC 1 dc 8 32 MHz Internal operating frequency fOP (fBus) — 8 MHz Internal clock period (1/fOP) tCYC 125 — ns RST input pulse width low tRL 50 — ns IRQ interrupt pulse width low (edge-triggered) tILIH 50 — ns IRQ interrupt pulse period tILIL Note(3) — tCYC Characteristic(1) Frequency of operation Crystal option External clock option(2) 1.
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Electrical Specifications 21.9 Clock Generation Module Characteristics 21.9.1 CGM Component Specifications Characteristic Symbol Min Typ Max Unit fXCLK 1 4 8 MHz Crystal load capacitance(1) CL — — — pF Crystal fixed capacitance C1 — (2 x CL) –5 — pF Crystal tuning capacitance C2 — (2 x CL) –5 — pF Feedback bias resistor RB 1 10 20 MΩ Symbol Min Typ Max Unit Reference frequency (for PLL operation) fRCLK 1 4 8 MHz Range nominal multiplier fNOM — 71.
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5.0-Volt ADC Characteristics 21.10 5.0-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 4.5 5.5 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –4 +4 LSB Includes quantization ADC internal clock fADIC 500 k 1.
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Electrical Specifications 21.11 3.3-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 3.0 3.6 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –6 +6 LSB Includes quantization ADC internal clock fADIC 500 k 1.
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5.0-Volt SPI Characteristics 21.12 5.
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Electrical Specifications 21.13 3.
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3.3-Volt SPI Characteristics SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
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Electrical Specifications SS INPUT 3 1 SPSCK INPUT CPOL = 0 5 4 2 SPSCK INPUT CPOL = 1 5 4 9 8 MISO INPUT SLAVE MSB OUT 6 BITS 6–1 7 MOSI OUTPUT NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 5 4 2 3 SPSCK INPUT CPOL = 1 8 MISO OUTPUT MOSI INPUT 5 4 10 NOTE 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not def
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Timer Interface Module Characteristics 21.14 Timer Interface Module Characteristics Characteristic Timer input capture pulse width Timer Input capture period Symbol Min Max Unit tTH, tTL 2 — tCYC tTLTL Note(1) — tCYC 1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC. tTLTL tTH INPUT CAPTURE RISING EDGE tTLTL tTL INPUT CAPTURE FALLING EDGE tTLTL tTH tTL INPUT CAPTURE BOTH EDGES Figure 21-4.
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Electrical Specifications 21.15 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz FLASH read bus clock frequency fRead(1) 0 — 8M Hz FLASH page erase time Limited endurance (<1 K cycles) Maximum endurance (>1 K cycles) tErase(2) 0.9 3.6 1 4 1.1 5.
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Chapter 22 Ordering Information and Mechanical Specifications 22.1 Introduction This section provides ordering information for the MC68HC908GZ16 along with the dimensions for: • 32-pin low-profile quad flat pack package (case 873A) • 48-pin low-profile quad flat pack (case 932-03) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Semiconductor Sales Office. 22.
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Appendix A MC68HC908GZ8 A.1 Introduction The MC68HC908GZ8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. The information contained in this document pertains to the MC68HC908GZ8 with the exceptions shown in this appendix. A.2 Block Diagram See Figure A-1. A.
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INTERNAL BUS 1–8 MHz OSCILLATOR PHASE LOCKED LOOP IRQ(3) VDDAD/VREFH VDDAD/VREFL SYSTEM INTEGRATION MODULE DDRA PTE5–PTE2 PTE1/RxD PTE0/TxD DDRB ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) 2-CHANNEL TIMER INTERFACE MODULE 2
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$0000 I/O REGISTERS 64 BYTES ↓ $003F $0040 RAM 1024 BYTES ↓ $043F $0440 UNIMPLEMENTED 192 BYTES ↓ $04FF $0500 ↓ MSCAN08 CONTROL AND MESSAGE BUFFER 128 BYTES SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 BREAK ADDRESS REGISTER HIGH (BRKH) $FE0A BREAK ADDRESS REGISTER LOW (BRKL) $FE0B BREAK STATUS AND CONTROL REGIST
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A.4 Ordering Information Table A-1.
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.