Datasheet

MSCAN08 Controller (MSCAN08)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
144 Freescale Semiconductor
WUPM — Wakeup Mode
This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from
spurious wakeups (see 12.8.5 Programmable Wakeup Function).
1 = MSCAN08 will wakeup the CPU only in cases of a dominant pulse on the bus which has a length
of at least t
wup
.
0 = MSCAN08 will wakeup the CPU after any recessive-to-dominant edge on the CAN bus.
CLKSRC — Clock Source
This flag defines which clock source the MSCAN08 module is driven from (see 12.10 Clock System).
1 = The MSCAN08 clock source is CGMOUT (see Figure 12-8).
0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 12-8).
NOTE
The CMCR1 register can be written only if the SFTRES bit in the MSCAN08
module control register is set
12.13.3 MSCAN08 Bus Timing Register 0
SJW1 and SJW0 — Synchronization Jump Width
The synchronization jump width (SJW) defines the maximum number of time quanta (T
q
) clock cycles
by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on
the bus (see Table 12-6).
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (T
q
) clock, which is used to build up the individual bit timing,
according to Table 12-7.
Address: $0502
Bit 7654321Bit 0
Read:
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Write:
Reset:00000000
Figure 12-18. Bus Timing Register 0 (CBTR0)
Table 12-6. Synchronization Jump Width
SJW1 SJW0
Synchronization
Jump Width
00
1 T
q
cycle
01
2 T
q
cycle
10
3 T
q
cycle
11
4 T
q
cycle