Datasheet

Programmer’s Model of Control Registers
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor 145
NOTE
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
12.13.4 MSCAN08 Bus Timing Register 1
SAMP — Sampling
This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per
bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For
higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit.
1 = Three samples per bit
(1)
0 = One sample per bit
TSEG22–TSEG10 — Time Segment
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point. Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in
Table 12-8.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (T
q
) clock cycles per bit as shown in Table 12-4).
NOTE
The CBTR1 register can only be written if the SFTRES bit in the MSCAN08
module control register is set.
Table 12-7. Baud Rate Prescaler
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Prescaler
Value (P)
000000 1
000001 2
000010 3
000011 4
:::::: :
:::::: :
111111 64
Address: $0503
Bit 7654321Bit 0
Read:
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Reset:00000000
Figure 12-19. Bus Timing Register 1 (CBTR1)
1. In this case PHASE_SEG1 must be at least 2 time quanta.
Bit time =
Pres value
f
MSCANCLK
• number of time quanta