Datasheet

Programmer’s Model of Control Registers
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor 153
AC7–AC0 — Acceptance Code Bits
AC7–AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related
identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is
then masked with the corresponding identifier mask register.
NOTE
The CIDAR0–CIDAR3 registers can be written only if the SFTRES bit in
CMCR0 is set
12.13.13 MSCAN08 Identifier Mask Registers (CIDMR0–CIDMR3)
The identifier mask registers specify which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. For standard identifiers it is required to program the last three bits
(AM2–AM0) in the mask register CIDMR1 to ‘don’t care’.
AM7–AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier
acceptance register must be the same as its identifier bit before a match will be detected. The message
will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit
in the identifier acceptance register will not affect whether or not the message is accepted.
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier bits.
NOTE
The CIDMR0–CIDMR3 registers can be written only if the SFTRES bit in
the CMCR0 is set
CIDMRO Address: $0514
Bit 7654321Bit 0
Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
Write:
Reset: Unaffected by reset
CIDMR1 Address: $0515
Bit 7654321Bit 0
Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
Write:
Reset: Unaffected by reset
CIDMR2 Address: $0516
Bit 7654321Bit 0
Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
Write:
Reset: Unaffected by reset
CIDMR3 Address: $0517
Bit 7654321Bit 0
Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
Write:
Reset: Unaffected by reset
Figure 12-28. Identifier Mask Registers
(CIDMR0–CIDMR3)