Datasheet

Port A
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor 159
Figure 13-4 shows the port A I/O logic.
Figure 13-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-2 summarizes the operation of the port A pins.
13.3.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the eight port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
Table 13-2. Port A Pin Functions
PTAPUE
Bit
DDRA
Bit
PTA
Bit
I/O Pin
Mode
Accesses to DDRA Accesses to PTA
Read/Write Read Write
10
X
(1)
1. X = Don’t care
Input, V
DD
(2)
2. I/O pin pulled up to V
DD
by internal pullup device
DDRA7–DDRA0 Pin
PTA7–PTA0
(3)
3. Writing affects data register, but does not affect input.
00X
Input, Hi-Z
(4)
4. Hi-Z = High impedance
DDRA7–DDRA0 Pin
PTA7–PTA0
(3)
X 1 X Output DDRA7–DDRA0 PTA7–PTA0 PTA7–PTA0
Address: $000D
Bit 7654321Bit 0
Read:
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:00000000
Figure 13-5. Port A Input Pullup Enable Register (PTAPUE)
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
DDRAx
PTAx
INTERNAL DATA BUS
V
DD
PTAPUEx
INTERNAL
PULLUP
DEVICE