Datasheet

Exception Control
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor 223
16.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
16.5.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 16-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 16-3. Interrupt Sources
Priority Interrupt Source Interrupt Status Register Flag
Highest Reset —
SWI instruction —
IRQ
pin I1
CGM clock monitor I2
TIM1 channel 0 I3
TIM1 channel 1 I4
TIM1 overflow I5
TIM2 channel 0 I6
TIM2 channel 1 I7
TIM2 overflow I8
SPI receiver full I9
SPI transmitter empty I10
SCI receive error I11
SCI receive I12
SCI transmit I13
Keyboard I14
ADC conversion complete I15
Timebase module I16
MSCAN08 wakeup I17
MSCAN08 error I18
MSCAN08 receive I19
Lowest MSCAN08 transmit I20