Datasheet

Computer Operating Properly (COP)
Technical Data MC68HC908LJ12 — Rev. 2.1
374 Computer Operating Properly (COP) Freescale Semiconductor
20.4.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
20.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
20.4.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
CONFIG1 register. (See Figure 20-2 and Section 5. Configuration
Registers (CONFIG).)
20.4.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the CONFIG1 register.
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS.
1 = COP time out period = 2
13
– 2
4
ICLK cycles
0 = COP time out period = 2
18
– 2
4
ICLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
Address: $001F
Bit 7654321Bit 0
Read:
COPRS LVISTOP LVIRSTD LVIPWRD
0
SSREC STOP COPD
Write:
Reset:00010000
= Unimplemented
Figure 20-2. Configuration Register 1 (CONFIG1)