Datasheet

MC68332 MOTOROLA

MC68332TS/D 65

6.2 Address Map

The “Access” column in the QSM address map below indicates which registers are accessible only at

the supervisor privilege level and which can be assigned to either the supervisor or user privilege level,

according to the value of the SUPV bit in the QSMCR.

Y = M111, where M is the logic state of the MM bit in the SIMCR.

Table 24 QSM Address Map

Access Address 15 8 7 0

S $YFFC00 QSM MODULE CONFIGURATION (QSMCR)

S $YFFC02 QSM TEST (QTEST)

S $YFFC04 QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR)

S/U $YFFC06 NOT USED

S/U $YFFC08 SCI CONTROL 0 (SCCR0)

S/U $YFFC0A SCI CONTROL 1 (SCCR1)

S/U $YFFC0C SCI STATUS (SCSR)

S/U $YFFC0E SCI DATA (SCDR)

S/U $YFFC10 NOT USED

S/U $YFFC12 NOT USED

S/U $YFFC14 NOT USED PQS DATA (PORTQS)

S/U $YFFC16 PQS PIN ASSIGNMENT (PQSPAR) PQS DATA DIRECTION (DDRQS)

S/U $YFFC18 SPI CONTROL 0 (SPCR0)

S/U $YFFC1A SPI CONTROL 1 (SPCR1)

S/U $YFFC1C SPI CONTROL 2 (SPCR2)

S/U $YFFC1E SPI CONTROL 3 (SPCR3) SPI STATUS (SPSR)

S/U $YFFC20–

$YFFCFF

NOT USED

S/U $YFFD00–

$YFFD1F

RECEIVE RAM (RR[0:F])

S/U $YFFD20–

$YFFD3F

TRANSMIT RAM (TR[0:F])

S/U $YFFD40–

$YFFD4F

COMMAND RAM (CR[0:F])

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