Freescale Semiconductor MPC7447AEC Rev. 5, 01/2006 Technical Data MPC7447A RISC Microprocessor Hardware Specifications This document is primarily concerned with the PowerPC™ MPC7447A; however, unless otherwise noted, all information here also applies to the MPC7447. The MPC7447A is an implementation of the PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors. This document describes pertinent electrical and physical characteristics of the MPC7447A.
Vector Integer Unit 2 L1 Service Queues Vector Integer Unit 1 +++ x÷ 32-Bit Integer Integer Integer Unit 122 Unit Unit (3) Integer Unit 2 32-Bit Reservation Reservation Reservation Station Station Station L2 Store Queue (L2SQ) Snoop Push/ Interventions L1 Castouts (4) Line Block 0 (32-Byte) Block 1 (32-Byte) Tags Status Status 32-Bit 16 Rename Buffers GPR File Vector Touch Queue FPR Issue (2-Entry/1-Issue) 512-Kbyte Unified L2 Cache Controller 128-Bit Dispatch Unit Instruction Queue (
Features NOTE The MPC7447A is a footprint-compatible, drop-in replacement in an MPC7447 application if the core power supply is 1.3 V. 2 Features This section summarizes features of the MPC7447A implementation of the PowerPC architecture. Major features of the MPC7447A are as follows: • High-performance, superscalar microprocessor — Up to four instructions can be fetched from the instruction cache at a time. — Up to 12 instructions can be in the instruction queue (IQ).
Features • • • • — Four vector units and 32-entry vector register file (VRs) – Vector permute unit (VPU) – Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add instructions (for example, vaddsbs, vaddshs, and vaddsws). – Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and vmladduhm).
Features • • • — Guarantees sequential programming model (precise exception model) — Monitors all dispatched instructions and retires them in order — Tracks unresolved branches and flushes instructions after a mispredicted branch — Retires as many as three instructions per clock cycle Separate on-chip L1 instruction and data caches (Harvard architecture) — 32-Kbyte, eight-way set-associative instruction and data caches — Pseudo least-recently-used (PLRU) replacement algorithm — 32-byte (eight-word) L1 c
Features • • • • • • – TLBs are hardware- or software-reloadable (that is, a page table search is performed in hardware or by system software on a TLB miss). Efficient data flow — Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits. — The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs. — The L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache.
Comparison with the MPC7447, MPC7445, and MPC7441 • 3 — IEEE 1149.1 JTAG interface — Array built-in self test (ABIST)—factory test only Reliability and serviceability — Parity checking on system bus — Parity checking on the L1 and L2 caches Comparison with the MPC7447, MPC7445, and MPC7441 Table 1 compares the key features of the MPC7447A with the key features of the earlier MPC7447, MPC7445, and MPC7441. All are based on the MPC7450 RISC microprocessor and are very similar architecturally.
Comparison with the MPC7447, MPC7445, and MPC7441 Table 1.
General Parameters Table 1. Microarchitecture Comparison (continued) Microarchitectural Specs MPC7447A MPC7447 Number of 32-byte sectors/line MPC7445 MPC7441 2 Parity Byte Thermal Control 4 Dynamic frequency switching (DFS) Yes No No No Thermal diode Yes No No No General Parameters The following list is a summary of the general parameters of the MPC7447A: Technology Die size Transistor count Logic design Packages Core power supply I/O power supply 5 0.13-μm CMOS, nine-layer metal 8.
Electrical and Thermal Characteristics Table 2. Absolute Maximum Ratings1 (continued) Characteristic Symbol Maximum Value Tstg –55 to 150 Storage temperature range Unit Notes °C — Notes: 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2.
Electrical and Thermal Characteristics Table 3. Input Threshold Voltage Settings BVSEL Signal Processor Bus Input Threshold is Relative to: Notes 0 1.8 V 1, 2 ¬HRESET Not available 1 HRESET 2.5 V 1 1 2.5 V 1 Notes: 1. Caution: The input threshold selection must agree with the OV DD voltages supplied. See notes in Table 2. 2. If used, pull-down resistors should be less than 250 Ω. Table 4 provides the recommended operating conditions for the MPC7447A.
Electrical and Thermal Characteristics Table 5. Package Thermal Characteristics1 (continued) Characteristic Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board Symbol Value Unit Notes RθJMA 16 °C/W 2, 4 Junction-to-board thermal resistance RθJB 10 °C/W 5 Junction-to-case thermal resistance RθJC < 0.1 °C/W 6 Notes: 1. Refer to Section 9.8, “Thermal Management Information,” for details about thermal management. 2.
Electrical and Thermal Characteristics Table 6. DC Electrical Specifications (continued) At recommended operating conditions. See Table 4. Nominal Bus Voltage 1 Characteristic Capacitance, Vin = 0 V, f = 1 MHz Symbol Min Max Unit Notes Cin — 8.0 pF 5 All other inputs Notes: 1. Nominal voltages; see Table 4 for recommended operating conditions. 2. For processor bus signals, the reference is OVDD 3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals 4.
Electrical and Thermal Characteristics Table 7. Power Consumption for MPC7447A (continued) Processor (CPU) Frequency Typical 1000 1267 1333 5 1420 MHz 4.1 4.0 3.2 4.0 Unit Notes W 1, 2 Notes: 1. These values specify the power consumption for the core power supply (VDD) at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include I/O supply power (OVDD) or PLL supply power (AVDD).
Electrical and Thermal Characteristics Table 8. Clock AC Timing Specifications At recommended operating conditions. See Table 4.
Electrical and Thermal Characteristics 5.2.2 Processor Bus AC Specifications Table 9 provides the processor bus AC timing specifications for the MPC7447A as defined in Figure 4 and Figure 5. Table 9. Processor Bus AC Timing Specifications1 At recommended operating conditions. See Table 4.
Electrical and Thermal Characteristics Table 9. Processor Bus AC Timing Specifications1 (continued) At recommended operating conditions. See Table 4. All Speed Grades Symbol 2 Parameter SYSCLK to ARTRY/SHD0/SHD1 high impedance after precharge Unit tKHARPZ Min Max — 2 Notes tSYSCLK 3, 5, 6, 7 Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK.
Electrical and Thermal Characteristics Figure 5 provides the mode select input timing diagram for the MPC7447A. The mode select inputs are sampled twice, once before and once after HRESET negation. VM VM SYSCLK HRESET Mode Signals 2nd Sample 1st Sample VM = Midpoint Voltage (OV DD/2) Figure 5. Mode Input Sample Timing Diagram Figure 6 provides the input/output timing diagram for the MPC7447A.
Electrical and Thermal Characteristics 5.2.3 IEEE 1149.1 AC Timing Specifications Table 10 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 16 through Figure 19. Table 10. JTAG AC Timing Specifications (Independent of SYSCLK)1 At recommended operating conditions. See Table 4. Parameter Symbol Min Max Unit TCK frequency of operation fTCLK 0 33.3 MHz TCK cycle time tTCLK 30 — ns TCK clock pulse width measured at 1.
Electrical and Thermal Characteristics Figure 8 provides the JTAG clock input timing diagram. TCLK VM VM VM tJHJL tJR tJF tTCLK VM = Midpoint Voltage (OVDD/2) Figure 8. JTAG Clock Input Timing Diagram Figure 9 provides the TRST timing diagram. VM VM TRST tTRST VM = Midpoint Voltage (OVDD/2) Figure 9. TRST Timing Diagram Figure 10 provides the boundary-scan timing diagram.
Electrical and Thermal Characteristics Figure 11 provides the test access port timing diagram. TCK VM VM tIVJH tIXJH Input Data Valid TDI, TMS tJLOV tJLOX Output Data Valid TDO tJLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Figure 11. Test Access Port Timing Diagram 5.
Pin Assignments 6 Pin Assignments Figure 12 (in Part A) shows the pinout of the MPC7447A, 360 high coefficient of thermal expansion ceramic ball grid array (HCTE) package as viewed from the top surface. Part B shows the side profile of the HCTE package to indicate the direction of the top surface view. Part A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B C D E F G H J K L M N P R T U V W Not to Scale Part B Substrate Assembly Encapsulant View Die Figure 12.
Pinout Listings 7 Pinout Listings Table 12 provides the pinout listing for the MPC7447A, 360 HCTE package. The pinouts of the MPC7447A and MPC7447 are pin compatible, but there have been some changes. An MPC7447A may be populated on a board designed for a MPC7447 provided all pins defined as ‘no connect’ for the MPC7447 are unterminated as required by the MPC7457 RISC Microprocessor Hardware Specifications.
Pinout Listings Table 12.
Pinout Listings Table 12.
Pinout Listings Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued) Signal Name VDD_SENSE Pin Number G13, N12 Active I/O I/F Select1 Notes — — N/A 18 Notes: 1. OVDD supplies power to the processor bus, JTAG, and all control signals; VDD supplies power to the processor core and the PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8 V), or to HRESET or OVDD (selects 2.5 V); see Table 3.
Package Description 8 Package Description The following sections provide the package parameters and mechanical dimensions for the HCTE package. 8.1 Package Parameters for the MPC7447A, 360 HCTE BGA The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead high coefficient of thermal expansion ceramic ball grid array (HCTE).
Package Description 8.2 Mechanical Dimensions for the MPC7447A, 360 HCTE BGA Figure 13 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447A, 360 HCTE BGA package. 2X 0.2 D Capacitor Region B D1 D3 A1 CORNER D2 A 1 0.15 A NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters. 3. Top side A1 corner index is a metalized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array.
Package Description 8.3 Package Parameters for the MPC7447A, 360 HCTE LGA The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360 high coefficient of thermal expansion ceramic land grid array (HCTE). Package outline Interconnects Pitch Minimum module height Maximum module height Coefficient of thermal expansion 25 × 25 mm 360 (19 × 19 ball array – 1) 1.27 mm (50 mil) 1.92 mm 2.20 mm 12.3 ppm/°C MPC7447A RISC Microprocessor Hardware Specifications, Rev.
Package Description 8.4 Mechanical Dimensions for the MPC7447A, 360 HCTE LGA Figure 14 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447A, 360 HCTE LGA package. 2X 0.2 D Capacitor Region B D1 D3 A1 CORNER D2 A 1 0.15 A NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters. 3. Top side A1 corner index is a metalized feature with various shapes. Bottom side A1 corner is designated with a pad missing from the array.
Package Description 8.5 Package Parameters for the MPC7447A, 360 HCTE RoHS-Compliant BGA The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360 lead-free high coefficient of thermal expansion ceramic ball grid array (HCTE). Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter Coefficient of thermal expansion 25 × 25 mm 360 (19 × 19 ball array – 1) 1.27 mm (50 mil) 2.32 mm 2.80 mm 0.75 mm (30 mil) 12.
Package Description 8.6 Mechanical Dimensions for the MPC7447A, 360 HCTE RoHS-Compliant BGA Figure 15 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447A, 360 HCTE BGA package. 2X 0.2 D Capacitor Region B D1 D3 A1 CORNER D2 A 1 0.15 A E3 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters. 3. Top side A1 corner index is a metalized feature with various shapes.
Package Description 8.7 Substrate Capacitors for the MPC7447A, 360 HCTE Figure 16 shows the connectivity of the substrate capacitor pads for the MPC7447A, 360 HCTE. All capacitors are 100 nF.
System Design Information 9 System Design Information This section provides system and thermal design recommendations for successful application of the MPC7447A. 9.1 9.1.1 Clocks PLL Configuration The MPC7447A PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the MPC7447A is shown in Table 13 for a set of example frequencies.
System Design Information Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts (continued) Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_ CFG[0:4] Bus-toCore Multiplier Core-toVCO Multiplier 01100 8.5x 2x 01111 9x 2x 01110 9.
System Design Information Table 13.
System Design Information Table 14. Spread Specturm Clock Source Recommendations At recommended operating conditions. See Table 4. Parameter Min Max Unit Notes Frequency modulation — 50 kHz 1 Frequency spread — 1.0 % 1, 2 Notes: 1. Guaranteed by design. 2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the minimum and maximum specifications given in Table 8.
System Design Information These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT) capacitors should be used to minimize lead inductance. Orientations where connections are made along the length of the part, such as 0204, are preferable but not mandatory. Consistent with the recommendations of Dr.
System Design Information OVDD RN SW2 Data Pad SW1 RP OGND Figure 18. Driver Impedance Measurement Table 15 summarizes the signal impedance results. The impedance increases with junction temperature and is relatively unaffected by bus voltage. Table 15. Impedance Characteristics VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C Impedance Z0 9.6 Processor Bus Unit Typical 33–42 Ω Maximum 31–51 Ω Pull-Up/Pull-Down Resistor Requirements The MPC7447A requires high-resistive (weak: 4.
System Design Information During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7447A must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the MPC7447A or by other receivers in the system.
System Design Information The COP header shown in Figure 19 adds many benefits—breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface—and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header).
System Design Information From Target Board Sources (if any) SRESET SRESET HRESET HRESET 6 QACK 13 11 HRESET 10 KΩ SRESET 10 KΩ OVDD OVDD 10 KΩ OVDD 10 KΩ OVDD 0Ω5 1 2 3 4 5 6 7 8 9 10 11 12 6 5 10 KΩ OVDD OVDD CHKSTP_OUT CHKSTP_OUT Key 14 2 10 KΩ OVDD OVDD CHKSTP_IN COP Header COP Connector Physical Pin Out 2 KΩ 10 KΩ KEY 16 VDD_SENSE 1 15 13 No Pin 15 TRST 6 TRST 4 CHKSTP_IN 8 TMS 9 1 3 TMS TDO TDO TDI TDI TCK 7 2 10 12 16 TCK QACK QACK NC NC 2 KΩ 3
System Design Information 9.8 Thermal Management Information This section provides thermal management information for the high coefficient of thermal expansion (HCTE) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. The MPC7447A implements several features designed to assist with thermal management, including DFS and the temperature diode.
System Design Information Heat Sink HCTE LGA Package Heat Sink Clip Thermal Interface Material Printed-Circuit Board Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options The board designer can choose between several types of heat sinks to place on the MPC7447A. There are several commercially-available heat sinks for the MPC7447A provided by the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.
System Design Information 9.8.1 Internal Package Conduction Resistance For the exposed-die packaging technology described in Table 5, the intrinsic conduction thermal resistance paths are as follows: • The die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die) • The die junction-to-board thermal resistance Figure 22 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
System Design Information the selection of any thermal interface material depends on many factors—thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and so on. Silicone Sheet (0.006 in.) Bare Joint Fluoroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Specific Thermal Resistance (K-in.2/W) 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) Figure 23.
System Design Information Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com 888-642-7674 Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 888-246-9050 The following section provides a heat sink selection example using one of the commercially available heat sinks. 9.8.
System Design Information heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on. Due to the complexity and variety of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely.
System Design Information 9.8.4 Temperature Diode The MPC7447A has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment.
System Design Information The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following: VH – VL = 1.986 × 10-4 × nT Solving for T, the equation becomes: nT = 9.8.5 VH – VL __________ 1.986 × 10-4 Dynamic Frequency Switching (DFS) The new DFS feature in the MPC7447A adds the ability to divide the processor-to-system bus ratio by two during normal functional operation by setting the HID1[DFS2] bit.
System Design Information Table 16. Valid Divide Ratio Configurations (continued) 9.8.5.3 Bus-to-Core Multiplier Configured by PLL_CFG[0:4] (see Table 13) Bus-to-Core Multiplier with HID1[DFS1] = 1 (÷2) 4x 2x 5x 2.5x 5.5x N/A 6x 3x 6.5x N/A 7x 3.5x 7.5x N/A 8x 4x 8.5x N/A 9x 4.5x 9.5x N/A 10x 5x 10.5x N/A 11x 5.5x 11.5x N/A 12x 6x 12.5x N/A 13x 6.5x 13.5x N/A 14x 7x 15x 7.5x 16x 8x 17x 8.5x 18x 9x 20x 10x 21x 10.
Document Revision History 10 Document Revision History Table 17 provides a revision history for this hardware specification. Table 17. Document Revision History Revision Number Date Substantive Changes 5 01/30/2005 Corrected RoHS BGA sphere diameter dimensions 4 09/23/2005 Added RoHS BGA case outlines and part numbers. Removed note references for CI and WT in Table 12 3 08/23/2005 Added “Section 9.1.2, “System Bus Clock (SYSCLK) and Spread Spectrum Sources” Section 9.
Ordering Information 11.1 Part Numbers Fully Addressed by This Document Table 18 provides the Freescale part numbering nomenclature for the MPC7447A. Table 18. Part Numbering Nomenclature MC 7447A xx nnnn L x Product Code Part Identifier Package Processor Frequency Application Modifier Revision Level MC 7447A 11.2 HX = HCTE BGA VS = RoHS LGA VU = RoHS BGA 1000 1267 1333 1420 L: 1.3 V ± 50 mV 0 to 105°C B: 1.
Ordering Information Table 20. Part Numbers Addressed by MC7447ATxxnnnn N x Series Hardware Specification Addendum (Document Order No. MPC7447AECS02AD) MC 7447A T xx nnnn N x Product Code Part Identifier Specification Modifier Package Processor Frequency Application Modifier Revision Level MC 7447A T = Extended Temperature Device 11.3 HX = HCTE BGA 867 1000 1167 N: 1.1 V ± 50 mV –40 to 105°C B:1.1: PVR = 8003 0101 Part Marking Parts are marked as the example shown in Figure 25.
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