Datasheet
Table Of Contents
- 1 Overview
- 2 Features
- 3 Comparison with the MPC7447, MPC7445, and MPC7441
- 4 General Parameters
- 5 Electrical and Thermal Characteristics
- 6 Pin Assignments
- 7 Pinout Listings
- 8 Package Description
- 8.1 Package Parameters for the MPC7447A, 360 HCTE BGA
- 8.2 Mechanical Dimensions for the MPC7447A, 360 HCTE BGA
- 8.3 Package Parameters for the MPC7447A, 360 HCTE LGA
- 8.4 Mechanical Dimensions for the MPC7447A, 360 HCTE LGA
- 8.5 Package Parameters for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.6 Mechanical Dimensions for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.7 Substrate Capacitors for the MPC7447A, 360 HCTE
- 9 System Design Information
- 9.1 Clocks
- 9.2 PLL Power Supply Filtering
- 9.3 Decoupling Recommendations
- 9.4 Connection Recommendations
- 9.5 Output Buffer DC Impedance
- 9.6 Pull-Up/Pull-Down Resistor Requirements
- 9.7 JTAG Configuration Signals
- 9.8 Thermal Management Information
- Figure 20. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- 9.8.1 Internal Package Conduction Resistance
- 9.8.2 Thermal Interface Materials
- 9.8.3 Heat Sink Selection Example
- 9.8.4 Temperature Diode
- 9.8.5 Dynamic Frequency Switching (DFS)
- 10 Document Revision History
- 11 Ordering Information
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor 11
Electrical and Thermal Characteristics
Table 4 provides the recommended operating conditions for the MPC7447A.
NOTE
Table 4 describes the nominal operating conditions of the device. For
information regarding the operation of the device at supported derated core
voltage conditions, see Section 5.3, “Voltage and Frequency Derating.”
Table 5 provides the package thermal characteristics for the MPC7447A.
Table 3. Input Threshold Voltage Settings
BVSEL Signal Processor Bus Input Threshold is Relative to: Notes
0 1.8 V 1, 2
¬HRESET
Not available 1
HRESET
2.5 V 1
12.5 V1
Notes:
1. Caution: The input threshold selection must agree with the OV
DD
voltages supplied. See notes in Ta bl e 2 .
2. If used, pull-down resistors should be less than 250 Ω.
Table 4. Recommended Operating Conditions
1
Characteristic Symbol
Recommended Value
Unit Notes
Minimum Maximum
Core supply voltage V
DD
1.3 V ± 50 mV V 3
PLL supply voltage AV
DD
1.3 V ± 50 mV V 2, 3
Processor bus supply voltage BVSEL = 0 OV
DD
1.8 V ± 5% V
BVSEL = HRESET
or OV
DD
OV
DD
2.5 V ± 5%
Input voltage Processor bus V
in
GND OV
DD
V
JTAG signals V
in
GND OV
DD
Die-junction temperature T
j
0105°C
Notes:
1. These are the recommended and tested operating conditions. In addition, these devices also support voltage
derating; see Section 5.3, “Voltage and Frequency Derating.” Proper device operation outside of these conditions
and those specified in Section 5.3 is not guaranteed.
2. This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the
voltage at the AV
DD
pin, which may be reduced from V
DD
by the filter.
3. V
DD
and AV
DD
may be reduced in order to reduce power consumption if further maximum core frequency
constraints are observed. See Section 5.3, “Voltage and Frequency Derating,” for specific information.
Table 5. Package Thermal Characteristics
1
Characteristic Symbol Value Unit Notes
Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board R
θ
JA
26 °C/W 2, 3
Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board R
θ
JMA
19 °C/W 2, 4
Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board R
θ
JMA
20 °C/W 2, 4
