Datasheet
Table Of Contents
- 1 Overview
- 2 Features
- 3 Comparison with the MPC7447, MPC7445, and MPC7441
- 4 General Parameters
- 5 Electrical and Thermal Characteristics
- 6 Pin Assignments
- 7 Pinout Listings
- 8 Package Description
- 8.1 Package Parameters for the MPC7447A, 360 HCTE BGA
- 8.2 Mechanical Dimensions for the MPC7447A, 360 HCTE BGA
- 8.3 Package Parameters for the MPC7447A, 360 HCTE LGA
- 8.4 Mechanical Dimensions for the MPC7447A, 360 HCTE LGA
- 8.5 Package Parameters for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.6 Mechanical Dimensions for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.7 Substrate Capacitors for the MPC7447A, 360 HCTE
- 9 System Design Information
- 9.1 Clocks
- 9.2 PLL Power Supply Filtering
- 9.3 Decoupling Recommendations
- 9.4 Connection Recommendations
- 9.5 Output Buffer DC Impedance
- 9.6 Pull-Up/Pull-Down Resistor Requirements
- 9.7 JTAG Configuration Signals
- 9.8 Thermal Management Information
- Figure 20. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- 9.8.1 Internal Package Conduction Resistance
- 9.8.2 Thermal Interface Materials
- 9.8.3 Heat Sink Selection Example
- 9.8.4 Temperature Diode
- 9.8.5 Dynamic Frequency Switching (DFS)
- 10 Document Revision History
- 11 Ordering Information
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor 13
Electrical and Thermal Characteristics
Table 7 provides the power consumption for the MPC7447A. For information regarding power
consumption when dynamic frequency switching is enabled, see Section 9.8.5, “Dynamic Frequency
Switching (DFS).”
NOTE
The power consumption information in this table applies when the device is
operated at the nominal core voltage indicated in Table 4. For power
consumption at derated core voltage conditions, see Section 5.3, “Voltage
and Frequency Derating.”
Capacitance,
V
in
=
0 V, f = 1 MHz
All other inputs C
in
—8.0pF5
Notes:
1. Nominal voltages; see Table 4 for recommended operating conditions.
2. For processor bus signals, the reference is OV
DD
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals
4. The leakage is measured for nominal OV
DD
and V
DD
, or both OV
DD
and V
DD
must vary in the same direction (for
example, both OV
DD
and V
DD
vary by either +5% or –5%).
5. Capacitance is periodically sampled rather than 100% tested.
6. Excludes signals with internal pullups: BVSEL, LSSD_MODE
, TDI, TMS, and TRST.
Table 7. Power Consumption for MPC7447A
Processor (CPU) Frequency
Unit Notes
1000 1267 1333
5
1420 MHz
Full-Power Mode
Typical 16.0 18.3 18.0 21.0 W 1, 2
Maximum 23.0 26.0 25.0 30.0 W 1, 3
Nap Mode
Typical 4.1 4.1 3.3 4.1 W 1, 2
Sleep Mode
Typical 4.1 4.1 3.3 4.1 W 1, 2
Deep Sleep Mode (PLL Disabled)
Table 6. DC Electrical Specifications (continued)
At recommended operating conditions. See Table 4.
Characteristic
Nominal
Bus
Vol tag e
1
Symbol Min Max Unit Notes
