Datasheet

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
16 Freescale Semiconductor
Electrical and Thermal Characteristics
5.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7447A as defined in Figure 4 and
Figure 5.
Table 9. Processor Bus AC Timing Specifications
1
At recommended operating conditions. See Table 4.
Parameter Symbol
2
All Speed Grades
Unit Notes
Min Max
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK
, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK
, TA, TBEN, TEA, TS, EXT_QUAL,
PMON_IN
, SHD[0:1]
BMODE
[0:1], BVSEL
t
AVKH
t
DVKH
t
IVKH
t
MVKH
1.8
1.8
1.8
1.8
—
—
—
—
ns
—
—
—
8
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK
, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK
, TA, TBEN, TEA, TS, EXT_QUAL,
PMON_IN
, SHD[0:1]
BMODE
[0:1], BVSEL
t
AXKH
t
DXKH
t
IXKH
t
MXKH
0
0
0
0
—
—
—
—
ns
—
—
—
—
8
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK
, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,
PMON_OUT
, QREQ, TBST, TSIZ[0:2], TT[0:3], WT
TS
ARTRY, SHD[0:1]
t
KHAV
t
KHDV
t
KHOV
t
KHTSV
t
KHARV
—
—
—
—
—
2.0
2.0
2.0
2.0
2.0
ns
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK
, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,
PMON_OUT
, QREQ, TBST, TSIZ[0:2], TT[0:3], WT
TS
ARTRY, SHD[0:1]
t
KHAX
t
KHDX
t
KHOX
t
KHTSX
t
KHARX
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
ns
SYSCLK to output enable t
KHOE
0.5 — ns 5
SYSCLK to output high impedance (all except TS
, ARTRY,
SHD0
, SHD1)
t
KHOZ
—3.5ns5
SYSCLK to TS
high impedance after precharge t
KHTSPZ
—1t
SYSCLK
3, 4, 5
Maximum delay to ARTRY
/SHD0/SHD1 precharge t
KHARP
—1t
SYSCLK
3, 5, 6, 7