Datasheet
Table Of Contents
- 1 Overview
- 2 Features
- 3 Comparison with the MPC7447, MPC7445, and MPC7441
- 4 General Parameters
- 5 Electrical and Thermal Characteristics
- 6 Pin Assignments
- 7 Pinout Listings
- 8 Package Description
- 8.1 Package Parameters for the MPC7447A, 360 HCTE BGA
- 8.2 Mechanical Dimensions for the MPC7447A, 360 HCTE BGA
- 8.3 Package Parameters for the MPC7447A, 360 HCTE LGA
- 8.4 Mechanical Dimensions for the MPC7447A, 360 HCTE LGA
- 8.5 Package Parameters for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.6 Mechanical Dimensions for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.7 Substrate Capacitors for the MPC7447A, 360 HCTE
- 9 System Design Information
- 9.1 Clocks
- 9.2 PLL Power Supply Filtering
- 9.3 Decoupling Recommendations
- 9.4 Connection Recommendations
- 9.5 Output Buffer DC Impedance
- 9.6 Pull-Up/Pull-Down Resistor Requirements
- 9.7 JTAG Configuration Signals
- 9.8 Thermal Management Information
- Figure 20. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- 9.8.1 Internal Package Conduction Resistance
- 9.8.2 Thermal Interface Materials
- 9.8.3 Heat Sink Selection Example
- 9.8.4 Temperature Diode
- 9.8.5 Dynamic Frequency Switching (DFS)
- 10 Document Revision History
- 11 Ordering Information
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
2 Freescale Semiconductor
Overview
Figure 1. MPC7447A Block Diagram
+
Integer
Reservation
Station
Unit 2
+
Integer
Reservation
Station
Unit 2
Additional Features
• Time Base Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
• Dynamic Frequency Switching (DFS)
• Temperature Diode
+
+
x ÷
FPSCR
FPSCR
PA
+ x ÷
Instruction Unit
Instruction Queue
(12-Word)
96-Bit (3 Instructions)
Reservation
Integer
128-Bit (4 Instructions)
32-Bit
Floating-
Point Unit
64-Bit
Reservation
Load/Store Unit
(EA Calculation)
Finished
32-Bit
(16-Entry)
Tags
32-Kbyte
D Cache
36-Bit
64-Bit
Integer
Stations (2)
Reservation
Station
Reservation
Stations (2)
FPR File
16 Rename
Buffers
Stations (2-Entry)
GPR File
16 Rename
Buffers
Reservation
Station
VR File
16 Rename
Buffers
64-Bit
128-Bit
128-Bit
Completed
Instruction MMU
SRs
(Shadow)
128-Entry
IBAT Array
ITLB
Ta g s
32-Kbyte
I Cache
Stores
Stores
Load Miss
Vector
Touch
Queue
(3)
VR Issue FPR Issue
Branch Processing Unit
CTR
LR
BTIC (128-Entry)
BHT (2048-Entry)
Fetcher
GPR Issue
(6-Entry/3-Issue) (4-Entry/2-Issue) (2-Entry/1-Issue)
Dispatch
Unit
Data MMU
SRs
(Original)
128-Entry
DBAT Array
DTLB
Vector Touch Engine
32-Bit
EA
L1 Castout
Status
L2 Store Queue (L2SQ)
Vector
FPU
Reservation
Station
Reservation
Station
Reservation
Station
Vector
Integer
Unit 1
Vector
Integer
Unit 2
Vector
Permute
Unit
Line
Tags
Block 0 (32-Byte)
Status
Block 1 (32-Byte)
Memory Subsystem
Snoop Push/
Interventions
L1 Castouts
Bus Accumulator
L1 Push
(4)
Unit 2 Unit 1
L1 Load Queue (LLQ)
L1 Load Miss (5)
Cacheable Store Miss (1)
Instruction Fetch (2)
L1 Service
L1 Store Queue
(LSQ)
System Bus Interface
L2 Prefetch (3)
Address Bus Data Bus
Queues
Castout
Bus Store Queue
Push
Load
Queue (11)
Queue (5) /
Queue (6)
1
The Castout Queue and Push Queue share resources such that they have a combined total of 6 entries.
The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.
512-Kbyte Unified L2 Cache Controller
Notes:
Completion Queue
Completion Unit
Completes up
to three
per clock
instructions