Datasheet
Table Of Contents
- 1 Overview
- 2 Features
- 3 Comparison with the MPC7447, MPC7445, and MPC7441
- 4 General Parameters
- 5 Electrical and Thermal Characteristics
- 6 Pin Assignments
- 7 Pinout Listings
- 8 Package Description
- 8.1 Package Parameters for the MPC7447A, 360 HCTE BGA
- 8.2 Mechanical Dimensions for the MPC7447A, 360 HCTE BGA
- 8.3 Package Parameters for the MPC7447A, 360 HCTE LGA
- 8.4 Mechanical Dimensions for the MPC7447A, 360 HCTE LGA
- 8.5 Package Parameters for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.6 Mechanical Dimensions for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.7 Substrate Capacitors for the MPC7447A, 360 HCTE
- 9 System Design Information
- 9.1 Clocks
- 9.2 PLL Power Supply Filtering
- 9.3 Decoupling Recommendations
- 9.4 Connection Recommendations
- 9.5 Output Buffer DC Impedance
- 9.6 Pull-Up/Pull-Down Resistor Requirements
- 9.7 JTAG Configuration Signals
- 9.8 Thermal Management Information
- Figure 20. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- 9.8.1 Internal Package Conduction Resistance
- 9.8.2 Thermal Interface Materials
- 9.8.3 Heat Sink Selection Example
- 9.8.4 Temperature Diode
- 9.8.5 Dynamic Frequency Switching (DFS)
- 10 Document Revision History
- 11 Ordering Information
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
42 Freescale Semiconductor
System Design Information
Figure 19. JTAG Interface Connection
HRESET
HRESET
6
From Target
Board Sources
HRESET
13
SRESET
SRESET
SRESET
NC
NC
11
VDD_SENSE
6
5
1
15
2 KΩ
10 KΩ
10 KΩ
10 KΩ
OV
DD
OV
DD
OV
DD
OV
DD
CHKSTP_IN
CHKSTP_IN
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
COP Header
14
2
Key
QACK
OV
DD
OV
DD
10 KΩ
OV
DD
10 KΩ
OV
DD
10 KΩ
10 KΩ
QACK
QACK
CHKSTP_OUT
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No Pin
COP Connector
Physical Pin Out
10 KΩ
4
OV
DD
1
2 KΩ
3
0 Ω
5
Notes:
1. RUN/STOP
, normally found on pin 5 of the COP header, is not implemented on the MPC7447A. Connect
pin 5 of the COP header to OV
DD
with a 10-KΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK
.
4. Populate only if debug tool uses an open-drain type output and does not actively negate QACK
.
5. If the JTAG interface is implemented, connect HRESET
from the target source to TRST from the COP
header though an AND gate to TRST
of the part. If the JTAG interface is not implemented, connect
HRESET
from the target source to TRST of the part through a 0-Ω isolation resistor.
6. The COP port and target board should be able to independently assert HRESET
and TRST to the
processor in order to fully control the processor as shown above.
TRST
6
10 KΩ
OV
DD