Datasheet
Table Of Contents
- 1 Overview
- 2 Features
- 3 Comparison with the MPC7447, MPC7445, and MPC7441
- 4 General Parameters
- 5 Electrical and Thermal Characteristics
- 6 Pin Assignments
- 7 Pinout Listings
- 8 Package Description
- 8.1 Package Parameters for the MPC7447A, 360 HCTE BGA
- 8.2 Mechanical Dimensions for the MPC7447A, 360 HCTE BGA
- 8.3 Package Parameters for the MPC7447A, 360 HCTE LGA
- 8.4 Mechanical Dimensions for the MPC7447A, 360 HCTE LGA
- 8.5 Package Parameters for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.6 Mechanical Dimensions for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.7 Substrate Capacitors for the MPC7447A, 360 HCTE
- 9 System Design Information
- 9.1 Clocks
- 9.2 PLL Power Supply Filtering
- 9.3 Decoupling Recommendations
- 9.4 Connection Recommendations
- 9.5 Output Buffer DC Impedance
- 9.6 Pull-Up/Pull-Down Resistor Requirements
- 9.7 JTAG Configuration Signals
- 9.8 Thermal Management Information
- Figure 20. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- 9.8.1 Internal Package Conduction Resistance
- 9.8.2 Thermal Interface Materials
- 9.8.3 Heat Sink Selection Example
- 9.8.4 Temperature Diode
- 9.8.5 Dynamic Frequency Switching (DFS)
- 10 Document Revision History
- 11 Ordering Information
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
48 Freescale Semiconductor
System Design Information
heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level
interconnect technology, system air temperature rise, altitude, and so on.
Due to the complexity and variety of system-level boundary conditions for today's microelectronic
equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction)
may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as
well as system-level designs.
For system thermal modeling, the MPC7447A thermal model is shown in Figure 24. Four volumes
represent this device. Two of the volumes, solder ball-air and substrate, are modeled using the package
outline size of the package. The other two, die and bump-underfill, have the same size as the die. The
silicon die should be modeled 8.5 × 9.9 × 0.7 mm
3
with the heat source applied as a uniform source at the
bottom of the volume. The bump and underfill layer is modeled as 8.5 × 9.9 × 0.07 mm
3
(or as a collapsed
volume) with orthotropic material properties: 0.6 W/(m • K) in the xy-plane and 1.9 W/(m • K) in the
direction of the z-axis. The substrate volume is 25 × 25 × 1.2 mm
3
, and has 8.1 W/(m • K) isotropic
conductivity in the xy-plane and 4 W/(m • K) in the direction of the z-axis. The solder ball and air layer
are modeled with the same horizontal dimensions as the substrate and are 0.6 mm thick. They can also be
modeled as a collapsed volume using orthotropic material properties: 0.034 W/(m • K) in the xy-plane
direction and 3.8 W/(m • K) in the direction of the z-axis.
Figure 24. Recommended Thermal Model of MPC7447A
Bump and Underfill
Die
Substrate
Solder and Air
Die
Substrate
Side View of Model (Not to Scale)
Top View of Model (Not to Scale)
x
y
z
Conductivity Value Unit
Bump and Underfill (8.5 × 9.9 × 0.07 mm
3
)
k
x
0.6 W/(m • K)
k
y
0.6
k
z
1.9
Substrate (25 × 25 × 1.2 mm
3
)
k
x
8.1
k
y
8.1
k
z
4.0
Solder Ball and Air (25 × 25 × 0.6 mm
3
)
k
x
0.034
k
y
0.034
k
z
3.8
