Datasheet
Table Of Contents
- 1 Overview
- 2 Features
- 3 Comparison with the MPC7447, MPC7445, and MPC7441
- 4 General Parameters
- 5 Electrical and Thermal Characteristics
- 6 Pin Assignments
- 7 Pinout Listings
- 8 Package Description
- 8.1 Package Parameters for the MPC7447A, 360 HCTE BGA
- 8.2 Mechanical Dimensions for the MPC7447A, 360 HCTE BGA
- 8.3 Package Parameters for the MPC7447A, 360 HCTE LGA
- 8.4 Mechanical Dimensions for the MPC7447A, 360 HCTE LGA
- 8.5 Package Parameters for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.6 Mechanical Dimensions for the MPC7447A, 360 HCTE RoHS-Compliant BGA
- 8.7 Substrate Capacitors for the MPC7447A, 360 HCTE
- 9 System Design Information
- 9.1 Clocks
- 9.2 PLL Power Supply Filtering
- 9.3 Decoupling Recommendations
- 9.4 Connection Recommendations
- 9.5 Output Buffer DC Impedance
- 9.6 Pull-Up/Pull-Down Resistor Requirements
- 9.7 JTAG Configuration Signals
- 9.8 Thermal Management Information
- Figure 20. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options
- 9.8.1 Internal Package Conduction Resistance
- 9.8.2 Thermal Interface Materials
- 9.8.3 Heat Sink Selection Example
- 9.8.4 Temperature Diode
- 9.8.5 Dynamic Frequency Switching (DFS)
- 10 Document Revision History
- 11 Ordering Information
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor 51
System Design Information
9.8.5.3 Minimum Core Frequency Requirements with DFS
In many systems, enabling DFS can result in very low processor core frequencies. However, care must be
taken to ensure that the resulting processor core frequency is within the limits specified in Table 8. Proper
operation of the device is not guaranteed at core frequencies below the specified minimum f
core
.
4x 2x
5x 2.5x
5.5x N/A
6x 3x
6.5x N/A
7x 3.5x
7.5x N/A
8x 4x
8.5x N/A
9x 4.5x
9.5x N/A
10x 5x
10.5x N/A
11x 5.5x
11.5x N/A
12x 6x
12.5x N/A
13x 6.5x
13.5x N/A
14x 7x
15x 7.5x
16x 8x
17x 8.5x
18x 9x
20x 10x
21x 10.5x
24x 12x
28x 14x
Table 16. Valid Divide Ratio Configurations (continued)
Bus-to-Core Multiplier Configured
by PLL_CFG[0:4]
(see Table 13)
Bus-to-Core Multiplier with
HID1[DFS1] = 1
(
รท2)