Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 112 (20x20) 16-Bit 8 MHz I/O number 83

M68HC12

Microcontrollers

freescale.com

MC68HC812A4

Data Sheet

MC68HC812A4

Rev. 7

05/2006

Summary of content (242 pages)

PAGE 1
MC68HC812A4 Data Sheet M68HC12 Microcontrollers MC68HC812A4 Rev. 7 05/2006 freescale.
PAGE 2
PAGE 3
MC68HC812A4 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
PAGE 4
Revision History Revision History Date August, 2001 (Continued) September, 2001 August, 2002 Revision Level 4 5 6 Page Number(s) Description 12.11.3 Data Direction Register for Timer Port — Repetitive information removed. See 12.11.2 Timer Port Data Direction Register 209 18.12 Control Timing — Minimum values added for PWIRQ and PWTIM 329 18.14 Non-Multiplexed Expansion Bus Timing — Table heading changed to reflect minimum and maximum values at 8 MHz 334 Table 12-3.
PAGE 5
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Chapter 3 Central Processor Unit (CPU12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Chapter 4 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
List of Chapters MC68HC812A4 Data Sheet, Rev.
PAGE 7
Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . .
PAGE 8
Table of Contents 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.6.7 4.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12 6.3.13 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Direction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Direction Register. . . . . . . . . . . . . . . . . . . . .
PAGE 10
Table of Contents Chapter 9 Key Wakeups 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Key Wakeup Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 Port D Data Direction Register. . . . . . . . . .
PAGE 11
Chapter 12 Standard Timer Module 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Functional Description . . . . . . . . . . . .
PAGE 12
Table of Contents Chapter 13 Multiple Serial Interface (MSI) 13.1 13.2 13.3 13.4 13.5 13.6 13.6.1 13.6.2 13.6.3 13.6.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 13
14.8 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 14
Table of Contents Chapter 16 Analog-to-Digital Converter (ATD) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.
PAGE 15
Chapter 18 Electrical Characteristics 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 18.10 18.11 18.12 18.13 18.14 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 16
Table of Contents MC68HC812A4 Data Sheet, Rev.
PAGE 17
Chapter 1 General Description 1.1 Introduction The MC68HC812A4 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus.
PAGE 18
General Description • • • • • Two enhanced asynchronous non-return-to-zero (NRZ) serial communication interfaces (SCI) Enhanced synchronous serial peripheral interface (SPI) 8-channel, 8-bit analog-to-digital converter (ATD) Up to 24 key wakeup lines with interrupt capability Available in 112-lead low-profile quad flat pack (LQFP) packaging 1.3 Ordering Information The MC68HC812A4 is available in 112-lead low-profile quad flat pack (LQFP) packaging.
PAGE 19
Block Diagram 1.
PAGE 20
General Description 1.5 Signal Descriptions NOTE A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low.
PAGE 21
Signal Descriptions Table 1-2.
PAGE 22
General Description Table 1-2. Pin Descriptions (Continued) Pin Port Description RxD1 PS2 Receive pin for SCI1 TxD1 PS3 Transmit pin for SCI1 SDI/MISO PS4 Master in/slave out pin for SPI SDO/MOSI PS5 Master out/slave in pin for SPI SCK PS6 Serial clock for SPI SS PS7 Slave select output for SPI in master mode; slave select input in slave mode IOC7–IOC0 Port T Input capture or output compare channels and pulse accumulator input 1. The MCU operates from a single power supply.
PAGE 23
Signal Descriptions Table 1-4.
PAGE 24
General Description VDD VDD 4.
PAGE 25
Signal Descriptions A[0. . 21] A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 PE2/R/W PF6/CSP1 A0 PE3 5 4 3 2 1 44 43 42 27 26 25 24 21 20 19 18 17 16 40 39 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 U4 IDT71016 WE CS BLE BHE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC VSS 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 33 34 D[0. . 15] VCC PF[0. . 7] PE[0. . 7] Figure 1-4.
PAGE 26
General Description VDD VDD 4 3 VDD VSS VDDX0 VDDX1 VSSX0 VSSX1 XFC VDDPLL VSSPLL RESET XTAL EXTAL PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 36 37 38 39 48 49 50 51 PE0/XIRQ PE1/IRQ PE2/R/W PE3/LSTRB PE4/ECLK PE5/MODA PE6/MODB PE7/ARST PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 97 98 99 100 101 102 103 104 BKGD/TAGHI PS0/RxD0 PS1/RxD0 PS2/TxD1 PS3/TxD12 PS4/SDI/MISO PS5/SD0/MOSI PS6/SCK PS7/SS PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 105 106 107 108 109 110 111 112 PT0/IOC0 PT1/IOC1 PT2/IOC2 PT3/IOC3 PT4/IOC4 PT5/IOC5 PT6/IO
PAGE 27
Signal Descriptions A[0. . 21] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 PF[0. . 7] 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 PF5/CSP0 22 24 PE2/R/W 31 1 U3 AM27F010 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 13 14 15 17 18 19 20 21 D8 D9 D10 D11 D12 D13 D14 D15 D[0. . 15] CE OE WE VPP PE[0. . 7] Figure 1-5. Expanded Narrow Mode SRAM Expansion Schematic (Sheet 2 of 3) D[0. .
PAGE 28
General Description MC68HC812A4 Data Sheet, Rev.
PAGE 29
Chapter 2 Register Block 2.1 Overview The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space by manipulating bits REG15–REG11 in the INITRG register. INITRG establishes the upper five bits of the register block’s 16-bit address. The register block occupies the first 512 bytes of the 2-Kbyte block. Figure 2-1 shows the default addressing. 2.2 Register Map Addr.
PAGE 30
Register Block Addr. $0007 $0008 $0009 $000A $000B $000C $000D Register Name Port D Data Direction Register (DDRD) See page 67. Port E Data Register (PORTE) See page 68. Port E Data Direction Register (DDRE) See page 68. Port E Assignment Register (PEAR) See page 69. Mode Register (MODE) See page 58. Pullup Control Register (PUCR) See page 71. Reduced Drive Register (RDRIV) See page 72.
PAGE 31
Register Map Addr. $0014 $0015 Register Name Bit 7 Real-Tme Interrupt Control Register (RTICTL) See page 105. Real-Time Interrupt Flag Register (RTIFLG) See page 107. Read: Write: Reset: Read: Write: Reset: $0016 COP Control Register (COPCTL) See page 107. Read: Write: Reset: $0017 $0018 Arm/Reset COP Register (COPRST) See page 109. Reserved $001E Interrupt Control Register (INTCR) See page 51.
PAGE 32
Register Block Addr. $0026 $0027 $0028 Register Name Port H Key Wakeup Interrupt Enable Register (KWIEH) See page 96. Port H Key Wakeup Flag Register (KWIFH) See page 96. Port J Data Register (PORTJ) See page 97. $0029 Port J Data Direction Register (DDRJ) See page 97. $002A Port J Key Wakeup Interrupt Enable Register (KWIEJ) See page 97. $002B $002C $002D $002E Port J Key Wakeup Flag Register (KWIFJ) See page 98. Port J Key Wakeup Polarity Register (KPOLJ) See page 98.
PAGE 33
Register Map Addr. $0033 $0034 $0035 $0036 $0037 $0038 Register Name Port G Data Direction Register (DDRG) See page 86. Data Page Register (DPAGE) See page 86. Program Page Register (PPAGE) See page 87. Extra Page Register (EPAGE) See page 87. Window Definition Register (WINDEF) See page 87. Memory Expansion Assignment Register (MXAR) See page 88.
PAGE 34
Register Block Addr. $0041 $0042 $0043 Register Name Loop Divider Register Low (LDVL) See page 113. Reference Divider Register High (RDVH) See page 114. Reference Divider Register Low (RDVL) See page 114.
PAGE 35
Register Map Addr. $0066 $0067 $0068 Register Name ATD Status Register 1 (ATDSTAT1) See page 204. ATD Status Register 2 (ATDSTAT2) See page 204. ATD Test Register 1 (ATDTEST1) See page 205. $0069 ATD Test Register 2 (ATDTEST2) See page 205.
PAGE 36
Register Block Addr. $0078 Register Name ATD Result Register 4 (ADR4H) See page 206. $0079 Reserved $007A ATD Result Register 5 (ADR5H) See page 206. $007B Reserved $007C ATD Result Register 6 (ADR6H) See page 206. $007D Reserved $007E ATD Result Register 7 (ADR7H) See page 206. $007F Reserved $0080 Timer IC/OC Select Register (TIOS) See page 125. $0081 Timer Compare Force Register (CFORC) See page 125. Timer Output Compare 7 Mask Register $0082 (OC7M) See page 126.
PAGE 37
Register Map Addr. $0086 Register Name Timer System Control Register (TSCR) See page 127. $0087 Reserved $0088 Timer Control Register 1 (TCTL1) See page 129. $0089 $008A $008B $008C $008D $008E $008F $0090 $0091 $0092 Timer Control Register 2 (TCTL2) See page 129. Timer Control Register 3 (TCTL3) See page 130. Timer Control Register 4 (TCTL4) See page 130. Timer Mask Register 1 (TMSK1) See page 130. Timer Mask Register 2 (TMSK2) See page 131. Timer Flag Register 1 (TFLG1) See page 132.
PAGE 38
Register Block Addr. $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E Register Name Timer Channel 1 Register Low (TC1L) See page 133. Timer Channel 2 Register High (TC2H) See page 133. Timer Channel 2 Register Low (TC2L) See page 133. Timer Channel 3 Register High (TC3H) See page 133. Timer Channel 3 Register Low (TC3L) See page 133. Timer Channel 4 Register High (TC4H) See page 133. Timer Channel 4 Register Low (TC4L) See page 133.
PAGE 39
Register Map Addr. $009F $00A0 $00A1 $00A2 $00A3 $00A4 Register Name Timer Channel 7 Register Low (TC7L) See page 133. Pulse Accumulator Control Register (PACTL) See page 134. Pulse Accumulator Flag Register (PAFLG) See page 135. Pulse Accumulator Counter Register High (PACNTH) See page 136. Pulse Accumulator Counter Register Low (PACNTL) See page 136. Reserved $00AD Timer Test Register (TIMTST) See page 137. $00B0 Timer Port Data Register (PORTT) See page 139.
PAGE 40
Register Block Addr. $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 Register Name SCI 0 Control Register 1 (SC0CR1) See page 169. SCI 0 Control Register 2 (SC0CR2) See page 171. SCI 0 Status Register 1 (SC0SR1) See page 172. SCI 0 Status Register 2 (SC0SR2) See page 173. SCI 0 Data Register High (SC0DRH) See page 174. SCI 0 Data Register Low (SC0DRL) See page 174. SCI 1 Baud Rate Register $00C8 High (SC1BDH) See page 168. SCI 1 Baud Rate Register $00C9 Low (SC1BDL) See page 168.
PAGE 41
Register Map Addr. $00CE $00CF $00D0 $00D1 $00D2 $00D3 Register Name Bit 7 SCI 1 Data Register High (SC1DRH) See page 174. SCI 1 Data Register Low (SC1DRL) See page 174. SPI 0 Control Register 1 (SP0CR1) See page 186. SPI 0 Control Register 2 (SP0CR2) See page 187. SPI Baud Rate Register (SP0BR) See page 188. SPI Status Register (SP0SR) See page 189. $00D4 Reserved $00D5 SPI Data Register (SP0DR) See page 190. $00D6 $00D7 $00D8 Port S Data Register (PORTS) See page 147.
PAGE 42
Register Block Addr. $00F2 $00F3 $00F4 ↓ $01FF Register Name EEPROM Test Register (EETST) See page 75. EEPROM Programming Register (EEPROG) See page 76. Read: Bit 7 6 5 4 3 2 1 Bit 0 EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0 0 0 0 0 0 0 0 0 BULKP 0 0 BYTE ROW ERASE EELAT EEPGM 1 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R R = Reserved Write: Reset: Read: Write: Reset: Reserved ↓ Reserved = Unimplemented U = Unaffected Figure 2-1.
PAGE 43
Chapter 3 Central Processor Unit (CPU12) 3.1 Overview The CPU12 is a high-speed, 16-bit processor unit. It has full 16-bit data paths and wider internal registers (up to 20 bits) for high-speed extended math instructions. The instruction set is a proper superset of the M68HC11instruction set. The CPU12 allows instructions with odd byte counts, including many single-byte instructions. This provides efficient use of ROM space.
PAGE 44
Central Processor Unit (CPU12) 3.3 CPU Registers This section describes the CPU registers. 3.3.1 Accumulators A and B Accumulators A and B are general-purpose 8-bit accumulators that contain operands and results of arithmetic calculations or data manipulations. Bit 7 6 5 4 3 2 1 Bit 0 A7 A6 A5 A4 A3 A2 A1 A0 Reset: Unaffected by reset Figure 3-2. Accumulator A (A) Bit 7 6 5 4 3 2 1 Bit 0 B7 B6 B5 B4 B3 B2 B1 B0 Reset: Unaffected by reset Figure 3-3.
PAGE 45
CPU Registers 3.3.3 Index Registers X and Y Index registers X and Y are used for indexed addressing. Indexed addressing adds the value in an index register to a constant or to the value in an accumulator to form the effective address of the operand. Index registers X and Y can also serve as temporary data storage locations. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 Reset: Unaffected by reset Figure 3-5.
PAGE 46
Central Processor Unit (CPU12) 3.3.6 Condition Code Register Reset: Bit 7 6 5 4 3 2 1 Bit 0 S X H I N Z V C 1 1 U 1 U U U U U = Unaffected Figure 3-9. Condition Code Register (CCR) S — Stop Disable Bit Setting the S bit disables the STOP instruction. X — XIRQ Interrupt Mask Bit Setting the X bit masks interrupt requests from the XIRQ pin. H — Half-Carry Flag The H flag is used only for BCD arithmetic operations.
PAGE 47
Addressing Modes 3.5 Addressing Modes Addressing modes determine how the CPU accesses memory locations to be operated upon. The CPU12 includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed addressing. Table 3-1 is a summary of the available addressing modes. Table 3-1. Addressing Mode Summary Addressing Mode Source Format Abbreviation Description Inherent INST INH Operands (if any) are in CPU registers.
PAGE 48
Central Processor Unit (CPU12) 3.6 Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode.
PAGE 49
Chapter 4 Resets and Interrupts 4.1 Introduction Resets and interrupts are exceptions. Each exception has a 16-bit vector that points to the memory location of the associated exception-handling routine. Vectors are stored in the upper 128 bytes of the standard 64-Kbyte address map. The six highest vector addresses are used for resets and non-maskable interrupt sources.
PAGE 50
Resets and Interrupts Table 4-1.
PAGE 51
Interrupt Registers 4.4 Interrupt Registers This section describes the interrupt registers. 4.4.1 Interrupt Control Register Address: $001E Read: Write: Reset: Bit 7 6 5 IRQE IRQEN DLY 1 1 0 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 4-1. Interrupt Control Register (INTCR) Read: Anytime Write: Varies from bit to bit IRQE — IRQ Edge-Sensitive-Only Bit IRQE can be written once in normal modes.
PAGE 52
Resets and Interrupts interrupt timer ($FFF0). If an unimplemented vector address or a non-I-masked vector address (a value higher than $F2) is written, then IRQ is the default highest priority interrupt. 4.5 Resets There are five possible sources of reset: 1. Power-on reset (POR) 2. External reset on the RESET pin 3. Reset from the alternate reset pin, ARST 4. The computer operating properly (COP) reset 5.
PAGE 53
Effects of Reset 4.6 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known startup states, as follows. 4.6.1 Operating Mode and Memory Map The states of the BGND, MODA, and MODB pins during reset determine the operating mode and default memory mapping. The SMODN, MODA, and MODB bits in the MODE register reflect the status of the mode-select inputs at the rising edge of reset.
PAGE 54
Resets and Interrupts 4.7 Interrupt Recognition Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared. When an interrupt request is recognized, the CPU responds at the completion of the instruction being executed. Interrupt latency varies according to the number of cycles required to complete the instruction. Some of the longer instructions can be interrupted and resume normally after servicing the interrupt.
PAGE 55
Chapter 5 Operating Modes and Resource Mapping 5.1 Introduction The MCU can operate in eight different modes. Each mode has a different default memory map and external bus configuration. After reset, most system resources can be mapped to other addresses by writing to the appropriate control registers. 5.2 Operating Modes The states of the BKGD, MODB, and MODA pins during reset determine the operating mode after reset.
PAGE 56
Operating Modes and Resource Mapping 5.2.1.1 Normal Expanded Wide Mode The 16-bit external address bus uses port A for the high byte and port B for the low byte. The 16-bit external data bus uses port C for the high byte and port D for the low byte. 5.2.1.2 Normal Expanded Narrow Mode The 16-bit external address bus uses port A for the high byte and port B for the low byte. The 8-bit external data bus uses port C. In this mode, 16-bit data is presented high byte first, followed by the low byte.
PAGE 57
Internal Resource Mapping commands can be executed while the CPU is operating normally. Other BDM commands are firmware based and require the BDM firmware to be enabled and active for execution. In special single-chip mode, BDM is enabled and active immediately out of reset. BDM is available in all other operating modes, but must be enabled before it can be activated. BDM should not be used in special peripheral mode because of potential bus conflicts.
PAGE 58
Operating Modes and Resource Mapping 5.4 Mode and Resource Mapping Registers This section describes the mode and resource mapping registers. 5.4.1 Mode Register MODE controls the MCU operating mode and various configuration options. This register is not in the map in peripheral mode.
PAGE 59
Mode and Resource Mapping Registers Normal modes: Write once Special modes: Write anytime except the first time EMD — Emulate Port D Bit This bit only has meaning in special expanded narrow mode. In expanded wide modes and special peripheral mode, PORTD, DDRD, KWIED, and KWIFD are removed from the memory map regardless of the state of this bit. In single-chip modes and normal expanded narrow mode, PORTD, DDRD, KWIED, and KWIFD are in the memory map regardless of the state of this bit.
PAGE 60
Operating Modes and Resource Mapping 5.4.3 RAM Initialization Register After reset, addresses of the 1-Kbyte RAM array begin at location $0800 but can be assigned to any 2-Kbyte boundary within the standard 64-Kbyte address space. Mapping of internal RAM is controlled by five bits in the INITRM register. The RAM array occupies the last 1 Kbyte of the 2-Kbyte block.
PAGE 61
Mode and Resource Mapping Registers 5.4.5 Miscellaneous Mapping Control Register Additional mapping controls are available that can be used in conjunction with memory expansion and chip selects. To use memory expansion, the part must be operated in one of the expanded modes. Sections of the standard 64-Kbyte memory map have memory expansion windows which allow more than 64 Kbytes to be addressed externally.
PAGE 62
Operating Modes and Resource Mapping 5.5 Memory Map Figure 5-6 illustrates the memory map for each mode of operation immediately after reset. $0000 $0000 EXT $01FF $0800 $0800 EXT $0BFF $1000 REGISTERS MAPPABLE TO ANY 2-K SPACE RAM MAPPABLE TO ANY 2-K SPACE $1000 EEPROM MAPPABLE TO ANY 4-K SPACE $2000 $1FFF EXT $F000 $F000 $FF00 $FFC0 $FFFF $FF00 EEPROM SINGLE-CHIP MODES BDM IF ACTIVE VECTORS EXPANDED VECTORS SINGLE-CHIP NORMAL VECTORS $FFFF $FFFF SINGLE-CHIP SPECIAL Figure 5-6.
PAGE 63
Chapter 6 Bus Control and Input/Output (I/O) 6.1 Introduction Internally the MCU has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be 8 or 16 bits. There are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the LSTRB signal to indicate 8-bit or 16-bit data. 6.2 Detecting Access Type from External Signals The external signals LSTRB, R/W, and A0 can be used to determine the type of bus access that is taking place.
PAGE 64
Bus Control and Input/Output (I/O) Port D and its associated data direction register may be removed from the on-chip map when port D is needed for 16-bit data transfers. If the MCU is in an expanded wide mode, port C and port D are used for 16-bit data and the associated port and data direction registers become external accesses. When the MCU is in expanded narrow mode, the external data bus is normally 8 bits.
PAGE 65
Registers 6.3.3 Port B Data Register Address: $0001 Read: Write: Reset: Expanded and peripheral: Bit 7 6 5 4 3 2 1 Bit 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 0 0 0 0 0 0 0 0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 Figure 6-3. Port B Data Register (PORTB) Read: Anytime, if register is in the map Write: Anytime, if register is in the map Bits PB7–PB0 correspond to address lines ADDR7–ADDR0.
PAGE 66
Bus Control and Input/Output (I/O) 6.3.5 Port C Data Register Address: $0004 Read: Write: Reset: Expanded wide and peripheral: Bit 7 6 5 4 3 2 1 Bit 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 0 0 0 0 0 0 0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA14/6 DATA13/5 DATA12/4 DATA11/3 DATA10/2 DATA9/1 DATA8/0 Expanded narrow: DATA15/7 Figure 6-5.
PAGE 67
Registers 6.3.7 Port D Data Register Address: $0005 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 0 0 0 0 0 0 Expanded wide and peripheral: DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Alternate pin function: KWD7 KWD6 KWD5 KWD4 KWD3 KWD2 KWD1 KWD0 Figure 6-7. Port D Data Register (PORTD) Read: Anytime, if register is in the map Write: Anytime, if register is in the map Bits PD7–PD0 correspond to data lines DATA7–DATA0.
PAGE 68
Bus Control and Input/Output (I/O) 6.3.9 Port E Data Register Address: $0008 Bit 7 6 5 4 3 2 1 Bit 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Normal narrow expanded: 0 0 0 0 1 0 0 0 All other modes: 0 0 0 0 0 0 0 0 ARST MODB or IPIPE1 MODA or IPIPE0 ECLK LSTRB R/W IRQ XIRQ Read: Write: Reset: Unaffected by reset Alternate pin function: Figure 6-9.
PAGE 69
Registers 6.3.11 Port E Assignment Register Address: $000A Bit 7 6 5 4 3 2 1 Bit 0 ARSIE PLLTE PIPOE NECLK LSTRE RDWE 0 0 Special single-chip: 0 0 1 0 1 1 0 0 Special expanded narrow: 0 0 1 0 1 1 0 0 Peripheral: 0 1 0 1 0 0 0 0 Special expanded wide: 0 0 1 0 1 1 0 0 Normal single-chip 0 0 0 1 0 0 0 0 Normal expanded narrow: 0 0 0 0 0 0 0 0 Normal expanded wide: 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 6-11.
PAGE 70
Bus Control and Input/Output (I/O) PIPOE — Pipe Status Signal Output Enable Bit Normal modes: Write once Special modes: Write anytime except the first time 1 = PE6 and PE5 are outputs and indicate the state of the instruction queue; no effect in single-chip modes. 0 = PE6 and PE5 are general-purpose I/O; if PLLTE = 1, PE6 is a test output signal from the PLL module.
PAGE 71
Registers 6.3.12 Pullup Control Register Address: $000C Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PUPH PUPG PUPF PUPE PUPD PUC PUPB PUPA 1 1 1 1 1 1 1 1 Figure 6-12. Pullup Control Register (PUCR) Read: Anytime, if register is in the map Write: Anytime, if register is in the map This register is not in the map in peripheral mode. These bits select pullup resistors for any pin in the corresponding port that is currently configured as an input.
PAGE 72
Bus Control and Input/Output (I/O) 6.3.13 Reduced Drive Register Address: $000D Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 RDPJ RDPH RDPG RDPF RDPE PRPD RDPC RDPAB 0 0 0 0 0 0 0 0 Figure 6-13. Reduced Drive Register (RDRIV) Read: Anytime, if register is in the map Write: Anytime, in normal modes; never in special modes This register is not in the map in peripheral mode. These bits select reduced drive for the associated port pins.
PAGE 73
Chapter 7 EEPROM 7.1 Introduction The MC68HC812A4 EEPROM (electrically erasable, programmable, read-only memory) serves as a 4096-byte nonvolatile memory which can be used for frequently accessed static data or as fast access program code. Operating system kernels and standard subroutines would benefit from this feature. The MC68HC812A4 EEPROM is arranged in a 16-bit configuration. The EEPROM array may be read as either bytes, aligned words, or misaligned words.
PAGE 74
EEPROM $_000 BPROT6 2 KBYTES $_800 BPROT5 1 KBYTE $_C00 BPROT4 512 BYTES $_E00 BPROT3 256 BYTES $_F00 BPROT2 128 BYTES SINGLE-CHIP VECTORS $_F80 BPROT1 64 BYTES RESERVED 64 BYTES $_FC0 BPROT0 64 BYTES VECTORS 64 BYTES $_FFF $FF80 $FFBF $FFC0 $FFFF Figure 7-1. EEPROM Block Protect Mapping 7.3 EEPROM Control Registers This section describes the EEPROM control registers. 7.3.
PAGE 75
EEPROM Control Registers 7.3.2 EEPROM Block Protect Register Address: $00F1 Bit 7 6 5 4 3 2 1 Bit 0 1 BPROT6 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0 1 1 1 1 1 1 1 1 Read: Write: Reset: Figure 7-3. EEPROM Block Protect Register (EEPROT) Read: Anytime Write: Anytime if EEPGM = 0 and PROTLCK = 0 This register prevents accidental writes to EEPROM. BPROT6–BPROT0 — EEPROM Block Protection Bit 0 = Associated EEPROM block can be programmed and erased.
PAGE 76
EEPROM EEVEN — Even Row Programming Bit 1 = Bulk program/erase all even rows 0 = Even row bulk programming/erasing disabled MARG — Program and Erase Voltage Margin Test Enable Bit 1 = Program and erase margin test 0 = Normal operation This bit is used to evaluate the program/erase voltage margin.
PAGE 77
EEPROM Control Registers Table 7-2. Erase Selection Byte Row Block Size 0 0 Bulk erase entire EEPROM array 0 1 Row erase 32 bytes 1 0 Byte or aligned word erase 1 1 Byte or aligned word erase ERASE — Erase Control Bit 1 = EEPROM configuration for erasure 0 = EEPROM configuration for programming Write anytime, if EEPGM = 0 This bit configures the EEPROM for erasure or programming.
PAGE 78
EEPROM MC68HC812A4 Data Sheet, Rev.
PAGE 79
Chapter 8 Memory Expansion and Chip-Select 8.1 Introduction To use memory expansion, the MCU must be operated in one of the expanded modes. Sections of the standard 64-Kbyte address space have memory expansion windows which allow an external address space larger than 64 Kbytes. Memory expansion consists of three memory expansion windows and six address lines which are used in addition to the standard 16 address lines. The memory expansion function reuses as many as six of the standard 16 address lines.
PAGE 80
Memory Expansion and Chip-Select Table 8-1.
PAGE 81
Generation of Chip-Selects CS3 can be used with a 1-Kbyte space in systems not using memory expansion. However, it must be made to appear as if memory expansion is in use. One of many possible configurations is: • Select the desired 1-Kbyte space for EPAGE (EWDIR in MISC in the MMI). • Write the EPAGE register with $0000, if EWDIR is one or $0001 if EWDIR is 0. • Designate all port G pins as I/O. • Enable EPAGE and CS3. • Make CS3 follow EPAGE. 8.2.
PAGE 82
Memory Expansion and Chip-Select INTERNAL SPACE EXTERNAL SPACE $0000 $0100 $0200 RAM 1 KBYTE $0300 $0400 $0500 CS3 $0600 1 KBYTE $0700 $0800 $0900 REGISTERS $0A00 CS0 256 BYTES CS1 128 BYTES CS2 128 BYTES $0B00 $0C00 $0D00 $0E00 $0F00 $0FFF Figure 8-1. Chip-Selects CS3–CS0 Partial Memory Map Table 8-2.
PAGE 83
Generation of Chip-Selects INTERNAL SPACE EXTERNAL SPACE CHIP-SELECT 3: (CS3) $0400 TO $07FF $0000 $1000 REGISTERS & RAM & CS[3:0] 0 1 2 PAGE 3 EEPROM DATA CHIP-SELECT: (CSD) $0000 TO $7FFF DATA WINDOW: $7000 to $7FFF $2000 ...
PAGE 84
Memory Expansion and Chip-Select 8.3 Chip-Select Stretch Each chip-select can be chosen to stretch bus cycles associated with it. Stretch can be zero, one, two, or three whole cycles added which allows interfacing to external devices which cannot meet full bus speed timing. Figure 8-3, Figure 8-4, Figure 8-5, and Figure 8-6 show the waveforms for zero to three cycles of stretch. INTERNAL E-CLOCK CS ECLK PIN UNSTRETCHED BUS CYCLE Figure 8-3.
PAGE 85
Memory Expansion Registers The external E-clock may be the stretched E-clock, the E-clock, or no clock depending on the selection of control bits ESTR and IVIS in the MODE register and NECLK in the PEAR register. 8.4 Memory Expansion Registers This section describes the memory expansion registers. 8.4.
PAGE 86
Memory Expansion and Chip-Select 8.4.3 Port F Data Direction Register Address: $0032 Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 0 0 0 0 0 0 0 = Unimplemented Figure 8-9. Port F Data Direction Register (DDRF) Read: Anytime Write: Anytime When port F is active, DDRF determines pin direction. 1 = Associated bit is an output. 0 = Associated bit is an input. 8.4.
PAGE 87
Memory Expansion Registers 8.4.6 Program Page Register Address: $0035 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PPA21 PPA20 PPA19 PPA18 PPA17 PPA16 PPA15 PPA14 0 0 0 0 0 0 0 0 Figure 8-12. Program Page Register (PPAGE) Read: Anytime Write: Anytime When enabled (PWEN = 1), the value in this register determines which of the 256 16-Kbyte pages is active in the program window.
PAGE 88
Memory Expansion and Chip-Select PWEN — Program Window Enable Bit 1 = Enables paging of the program space (16 Kbytes: $8000–$BFFF) via the PPAGE register 0 = Disables PPAGE EWEN — Extra Window Enable Bit 1 = Enables paging of the extra space (1 Kbyte) via the EPAGE register 0 = Disables EPAGE 8.4.9 Memory Expansion Assignment Register Address: $0038 Bit 7 6 0 0 Read: Write: Reset: 0 5 4 3 2 1 Bit 0 A21E A20E A19E A18E A17E A16E 0 0 0 0 0 0 0 = Unimplemented Figure 8-15.
PAGE 89
Chip-Select Registers 8.6 Chip-Select Registers This section describes the chip-select registers. 8.6.1 Chip-Select Control Register 0 Address: $003C Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 CSP1E CSP0E CSDE CS3E CS2E CS1E CS0E 0 1 0 0 0 0 0 = Unimplemented Figure 8-16. Chip-Select Control Register 0 (CSCTL0) Read: Anytime Write: Anytime Bits have no effect on the associated pin in single-chip modes.
PAGE 90
Memory Expansion and Chip-Select CS0E — Chip-Select 0 Enable Bit CS1, CS2, and CS3 have higher precedence and can override CS0 for portions of this space. 1 = Enables this chip-select which covers a 512-byte space following the register space ($x200–$x3FF or $xA00–$xBFF) 0 = Disables this chip-select 8.6.2 Chip-Select Control Register 1 Address: $003D Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 CSP1FL CSPA21 CSDHF CS3EP 0 0 0 0 2 1 Bit 0 0 0 0 0 0 0 = Unimplemented Figure 8-17.
PAGE 91
Chip-Select Registers 8.6.3 Chip-Select Stretch Registers Each of the seven chip-selects has a 2-bit field in this register which determines the amount of clock stretch for accesses in that chip-select space. Read: Anytime Write: Anytime Address: $003E Read: Bit 7 6 0 0 0 0 Write: Reset: 5 4 3 2 1 Bit 0 SRP1A SRP1B SRP0A SRP0B STRDA STRDB 1 1 1 1 1 1 = Unimplemented Figure 8-18.
PAGE 92
Memory Expansion and Chip-Select 8.7 Priority Only one module or chip-select may be selected at a time. If more than one module shares a space, only the highest priority module is selected. Table 8-5.
PAGE 93
Chapter 9 Key Wakeups 9.1 Introduction The key wakeup feature of the MC68HC812A4 issues an interrupt that wakes up the CPU when it is in stop or wait mode. Three ports are associated with the key wakeup function: port D, port H, and port J. Port D and port H wakeups are triggered with a falling signal edge. Port J key wakeups have a selectable falling or rising signal edge as the active edge.
PAGE 94
Key Wakeups 9.2.2 Port D Data Direction Register Address: $0007 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 9-2. Port D Data Direction Register (DDRD) Read: Anytime Write: Anytime This register is not in the map in wide expanded modes or in special expanded narrow mode with MODE register bit EMD set. Data direction register D is associated with port D and designates each pin as an input or output.
PAGE 95
Key Wakeup Registers 9.2.4 Port D Key Wakeup Flag Register Address: $0021 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 9-4. Port D Key Wakeup Flag Register (KWIFD) Read: Anytime Write: Anytime Each flag is set by a falling edge on its associated input pin. To clear the flag, write 1 to the corresponding bit in KWIFD.
PAGE 96
Key Wakeups 9.2.6 Port H Data Direction Register Address: $0025 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 0 0 0 0 0 0 0 0 Figure 9-6. Port H Data Direction Register (DDRH) Read: Anytime Write: Anytime Data direction register H is associated with port H and designates each pin as an input or output. DDRH7–DDRH0 — Data Direction Port H Bits 1 = Associated pin is an output. 0 = Associated pin is an input. 9.2.
PAGE 97
Key Wakeup Registers 9.2.9 Port J Data Register Address: $0028 Bit 7 6 5 4 3 2 1 Bit 0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 0 0 0 0 0 0 0 0 KWJ7 KWJ6 KWJ5 KWJ2 KWJ4 KWJ2 KWJ1 KWJ0 Read: Write: Reset: Alternate pin function: Figure 9-9. Port J Data Register (PORTJ) Read: Anytime Write: Anytime Port J is associated with key wakeup J. Key wakeups can be used with the pins designated as inputs or outputs. DDRJ determines whether each pin is an input or output. 9.2.
PAGE 98
Key Wakeups 9.2.12 Port J Key Wakeup Flag Register Address: $002B Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 KWIFJ7 KWIFJ6 KWIFJ5 KWIFJ4 KWIFJ3 KWIFJ2 KWIFJ1 KWIFJ0 0 0 0 0 0 0 0 0 Figure 9-12. Port J Key Wakeup Flag Register (KWIFJ) Read: Anytime Write: Anytime Each flag gets set by an active edge on the associated input pin. This could be a rising or falling edge based on the state of the KPOLJ register. To clear the flag, write 1 to the corresponding bit in KWIFJ.
PAGE 99
Key Wakeup Registers 9.2.14 Port J Pullup/Pulldown Select Register Address: $002D Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PUPSJ7 PUPSJ6 PUPSJ5 PUPSJ4 PUPSJ3 PUPSJ2 PUPSJ1 PUPSJ0 0 0 0 0 0 0 0 0 Figure 9-14. Port J Pullup/Pulldown Select Register (PUPSJ) Read: Anytime Write: Anytime Each bit in the register corresponds to a port J pin. Each bit selects a pullup or pulldown device for the associated port J pin.
PAGE 100
Key Wakeups MC68HC812A4 Data Sheet, Rev.
PAGE 101
Chapter 10 Clock Module 10.1 Introduction Clock generation circuitry generates the internal and external E-clock signals as well as internal clock signals used by the CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly (COP) watchdog circuit, and a periodic interrupt circuit are also incorporated into the MCU. 10.
PAGE 102
Clock Module Figure 10-2 shows clock timing relationships. Four bits in the CLKCTL register control the base clock and M-clock divide selection (÷1, ÷2, ÷4, and ÷8 are selectable). T1CLK T2CLK T3CLK T4CLK INTERNAL ECLK PCLK MCLK 1 MCLK 2 MCLK 4 MCLK 8 Note: The MCLK depends on the chosen divider settings in the CLKCTL register. Figure 10-2. Internal Clock Relationships 10.3 Register Map NOTE The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space.
PAGE 103
Functional Description 10.4 Functional Description This section provides a functional description of the MC68HC812A4. 10.4.1 Computer Operating Properly (COP) The COP or watchdog timer is an added check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping a free-running watchdog timer from timing out.
PAGE 104
Clock Module ÷ 8192 SCI0 BAUD RATE GENERATOR (³ 1 TO 8191) MCLK SCI0 RECEIVE BAUD RATE (16X) ÷ 16 SCI1 BAUD RATE GENERATOR (³ 1 TO 8191) SCI0 TRANSMIT BAUD RATE (1X) SCI1 RECEIVE BAUD RATE (16X) ÷ 16 SCI1 TRANSMIT BAUD RATE (1X) REGISTER: RTICTL BITS: RTR[2:1:0] 0:0:0 REGISTER: COPCTL BITS: CR[2:1:0] 0:0:0 0:0:1 0:0:1 ÷2 0:1:0 ÷4 0:1:0 ÷2 0:1:1 ÷4 0:1:1 ÷2 1:0:0 ÷4 1:0:0 ÷2 1:0:1 ÷4 1:0:1 ÷2 1:1:0 ÷4 1:1:0 ÷2 1:1:1 ÷4 1:1:1 TO COP TO RTI Figure 10-4.
PAGE 105
Registers and Reset Initialization PRS[4:0] PCLK 5-BIT ATD PRESCALER ÷2 ATD CLOCK REGISTER: SP0BR BITS: SPR2:SPR1:SPR0 0:0:0 SPI BIT RATE ÷2 0:0:1 ÷2 0:1:0 ÷2 0:1:1 ECLK BKGD IN SYNCHRONIZER ÷2 1:0:0 BKGD DIRECTION ÷2 1:0:1 ÷2 1:1:0 ÷2 1:1:1 BKGD PIN LOGIC BKGD OUT BDM BIT CLOCK Receive: Detect falling edge; count 12 E-clocks; sample input Transmit 1: Detect falling edge; count six E-clocks while output is high impedance; drive out one E cycle pulse high; return output to high impedanc
PAGE 106
Clock Module RTIE — Real-Time Interrupt Enable Bit Write: Anytime RTIE enables interrupt requests generated by the RTIF flag. 1 = RTIF interrupt requests enabled 0 = RTIF interrupt requests disabled RSWAI — RTI Stop in Wait Bit Write: Once in normal modes, anytime in special modes RSWAI disables the RTI and the COP during wait mode.
PAGE 107
Registers and Reset Initialization 10.5.2 Real-Time Interrupt Flag Register Address: $0015 Bit 7 Read: Write: Reset: RTIF 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-8. Real-Time Interrupt Flag Register (RTIFLG) RTIF — Real-Time Interrupt Flag RTIF is set when the timeout period elapses. RTIF generates an interrupt request if the RTIE bit is set in the RTI control register. Clear RTIF by writing to the real-time interrupt flag register with RTIF set.
PAGE 108
Clock Module FCM — Force Clock Monitor Reset Bit Write: Never in normal modes, anytime in special modes FCM forces a reset when the clock monitor is enabled and detects a slow or stopped clock. 1 = Clock monitor reset enabled 0 = Normal operation NOTE When the disable reset bit, DISR, is set, FCM has no effect. FCOP — Force COP Reset Bit Write: Never in normal modes; anytime in special modes FCOP forces a reset when the COP is enabled and times out.
PAGE 109
Registers and Reset Initialization 10.5.4 Arm/Reset COP Timer Register Address: $0017 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 0 Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: 0 0 0 0 0 0 0 0 Figure 10-10. Arm/Reset COP Timer Register (COPRST) To restart the COP timeout period and avoid a COP reset, write $55 and then $AA to this address before the end of the COP timeout period. Other instructions can be executed between these writes.
PAGE 110
Clock Module MC68HC812A4 Data Sheet, Rev.
PAGE 111
Chapter 11 Phase-Lock Loop (PLL) 11.1 Introduction The phase-lock loop (PLL) allows slight adjustments in the frequency of the MCU. The smallest increment of adjustment is ± 9.6 kHz to the output frequency (FOut) rate assuming an input clock of 16.8 MHz (OSCXTAL) and a reference divider set to 1750. Figure 11-1 shows the PLL dividers and a portion of the clock module and Figure 11-2 provides a register map. 11.
PAGE 112
Phase-Lock Loop (PLL) Table 11-1. PLL Filter Values RS E Clock CS 16,778.40524 8,000,000 0.000000033 32,000 11,864.12412 8,000,000 0.000000033 64,000 3,001.412373 8,000,000 0.000000033 1,000,000 2,450.642941 8,000,000 0.000000033 1,500,000 2,237.120698 8,000,000 0.000000033 1,800,000 2,122.319042 8,000,000 0.000000033 2,000,000 1,898.259859 8,000,000 0.000000033 2,500,000 1,732.866242 8,000,000 0.000000033 3,000,000 1,604.322397 8,000,000 0.000000033 3,500,000 1,500.
PAGE 113
Functional Description 11.4 Functional Description The PLL may be used to run the MCU from a different timebase than the incoming crystal value. If the PLL is selected, it continues to run when it’s in wait or stop mode which results in more power consumption than normal. To take full advantage of the reduced power consumption of stop mode, turn off the PLL before going into stop. Although it is possible to set the divider to command a very high clock frequency, do not exceed the 16.
PAGE 114
Phase-Lock Loop (PLL) 11.5.2 Reference Divider Registers Address: $0042 Read: Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 RDV11 RDV10 RDV9 RDV8 1 1 1 1 = Unimplemented Figure 11-5. Reference Divider Register High (RDVH) Address: $0043 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 RDV7 RDV6 RDV5 RDV4 RDV3 RDV2 RDV1 RDV0 1 1 1 1 1 1 1 1 Figure 11-6.
PAGE 115
Registers and Reset Initialization PLLS — PLL Select Bit (PLL output or crystal input frequency) PLLS selects the PLL after the LCKF flag is set. 1 = PLL selected 0 = Crystal input selected BCS[C:B:A] — Base Clock Select Bits These bits determine the frequency of SYSCLK. SYSCLK is the source clock for the MCU, including the CPU and buses. See Table 11-2. SYSCLK and is twice the bus rate. MUXCLK is either the PLL output or the crystal input frequency as selected by the PLLS bit. Table 11-2.
PAGE 116
Phase-Lock Loop (PLL) MC68HC812A4 Data Sheet, Rev.
PAGE 117
Chapter 12 Standard Timer Module 12.1 Introduction The standard timer module is a 16-bit, 8-channel timer with: • Input capture • Output compare • Pulse accumulator functions A block diagram is given in Figure 12-1. 12.2 Register Map A summary of the input/oputput (I/O) registers is shown in Figure 12-2. NOTE The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block.
PAGE 118
Standard Timer Module 12.3 Block Diagram CLK[1:0] PR[2:1:0] MODULE CLOCK PACLK PACLK/256 PACLK/65536 CHANNEL 7 OUTPUT COMPARE MUX TCRE PRESCALER CxI TIMCNTH:TIMCNTL CxF CLEAR COUNTER 16-BIT COUNTER TOF INTERRUPT LOGIC TOI TE INTERRUPT REQUEST CHANNEL 0 16-BIT COMPARATOR C0F EDGE DETECT IOS0 TIMC0H:TIMC0L 16-BIT LATCH EDG0A OM0 EDG0B OL0 CH. 0 CAPTURE PT0 LOGIC CH.
PAGE 119
Block Diagram Addr. $0080 $0081 Register Name Timer IC/OC Select Register (TIOS) See page 125. Timer Compare Force Register (CFORC) See page 125. Timer Output Compare 7 Mask Register $0082 (OC7M) See page 126. $0083 $0084 $0085 $0086 Timer Output Compare 7 Data Register (OC7D) See page 126. Timer Counter Register High (TCNTH) See page 127. Timer Counter Register Low (TCNTL) See page 127. Timer System Control Register (TSCR) See page 127.
PAGE 120
Standard Timer Module Addr. $008D $008E $008F $0090 $0091 $0092 $0093 $0094 $0095 $0096 $0097 $0098 Register Name Timer Mask Register 2 (TMSK2) See page 131. Timer Flag Register 1 (TFLG1) See page 132. Timer Flag Register 2 (TFLG2) See page 132. Timer Channel 0 Register High (TC0H) See page 133. Timer Channel 0 Register Low (TC0L) See page 133. Timer Channel 1 Register High (TC1H) See page 133. Timer Channel 1 Register Low (TC1L) See page 133. Timer Channel 2 Register High (TC2H) See page 133.
PAGE 121
Block Diagram Addr. $0099 $009A $009B $009C $009D $009E $009F Register Name Timer Channel 4 Register Low (TC4L) See page 133. Timer Channel 5 Register High (TC5H) See page 133. Timer Channel 5 Register Low (TC5L) See page 133. Timer Channel 6 Register High (TC6H) See page 133. Timer Channel 6 Register Low (TC6L) See page 133. Timer Channel 7 Register High (TC7H) See page 133. Timer Channel 7 Register Low (TC7L) See page 133. Pulse Accumulator Control $00A0 Register (PACTL) See page 134.
PAGE 122
Standard Timer Module Addr. $00AE $00AF Register Name Timer Port Data Register (PORTT) See page 139. Timer Port Data Direction Register (DDRT) See page 140. Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 Reset: Read: Write: Reset: Unaffected by reset Bit 7 5 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 = Unimplemented R = Reserved Figure 12-2. I/O Register Summary (Sheet 4 of 4) 12.
PAGE 123
Functional Description Setting a force output compare bit, FOCx, causes an immediate output compare on channel x. A forced output compare does not set the channel flag. An output compare on channel 7 overrides output compares on all other output compare channels. A channel 7 output compare causes any unmasked bits in the output compare 7 data register to transfer to the timer port data register. The output compare 7 mask register masks the bits in the output compare 7 data register.
PAGE 124
Standard Timer Module 12.4.4.2 Gated Time Accumulation Mode Setting the PAMOD bit configures the PA for gated time accumulation operation. An active level on the PAI pin enables a divided-by-64 clock to drive the PA. The PA edge bit, PEDGE, selects low levels or high levels to enable the divided-by-64 clock. The trailing edge of the active level at the PAI pin sets the PA input flag, PAIF. The PA input interrupt enable bit, PAI, enables the PAIF flag to generate interrupt requests.
PAGE 125
Registers and Reset Initialization 12.5 Registers and Reset Initialization This section describes the registers and reset initialization. 12.5.1 Timer IC/OC Select Register Address: $0080 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0 0 0 0 0 0 0 0 Figure 12-4.
PAGE 126
Standard Timer Module 12.5.3 Timer Output Compare 7 Mask Register Address: $0082 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 0 0 0 0 0 0 0 0 Figure 12-6. Timer Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime OC7M7–OC7M0 — Output Compare 7 Mask Bits Setting an OC7Mx bit configures the corresponding TIMPORT pin to be an output.
PAGE 127
Registers and Reset Initialization 12.5.5 Timer Counter Registers Address: $0084 Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 12-8. Timer Counter Register High (TCNTH) Address: $0085 Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 12-9.
PAGE 128
Standard Timer Module TSWAI — Timer Stop in Wait Mode Bit TSWAI disables the timer and PA in wait mode. 1 = Timer and PA disabled in wait mode 0 = Timer and PA enabled in wait mode NOTE If timer and PA interrupt requests are needed to bring the MCU out of wait mode, clear TSWAI before executing the WAIT instruction. TSBCK — Timer Stop in Background Mode Bit TSBCK stops the timer during background mode.
PAGE 129
Registers and Reset Initialization 12.5.7 Timer Control Registers 1 and 2 Address: $0088 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0 0 0 0 0 0 0 0 Figure 12-12. Timer Control Register 1 (TCTL1) Address: $0089 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 Figure 12-13.
PAGE 130
Standard Timer Module 12.5.8 Timer Control Registers 3 and 4 Address: $008A Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 Figure 12-14. Timer Control Register 3 (TCTL3) Address: $008B Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0 0 0 0 0 0 0 0 Figure 12-15.
PAGE 131
Registers and Reset Initialization 12.5.10 Timer Mask Register 2 Address: $008D Bit 7 Read: Write: Reset: 6 0 TOI 0 5 4 3 2 1 Bit 0 PUPT RDPT TCRE PR2 PR1 PR0 1 0 0 0 0 0 0 = Unimplemented Figure 12-17. Timer Mask 2 Register (TMSK2) Read: Anytime Write: Anytime TOI — Timer Overflow Interrupt Enable Bit TOI enables interrupt requests generated by the TOF flag.
PAGE 132
Standard Timer Module Table 12-3. Prescaler Selection (Continued) Value PR[2:1:0] Prescaler Divisor 5 101 32 6 110 32 7 111 32 NOTE The newly selected prescale divisor does not take effect until the next synchronized edge when all prescale counter stages equal 0. 12.5.11 Timer Flag Register 1 Address: $008E Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 Figure 12-18.
PAGE 133
Registers and Reset Initialization TOF — Timer Overflow Flag TOF is set when the timer counter rolls over from $FFFF to $0000. Clear TOF by writing a 1 to it. 1 = Timer overflow 0 = No timer overflow NOTE When the timer channel 7 registers contain $FFFF and the timer counter reset enable bit, TCRE, is set, TOF does not get set when the counter rolls over. NOTE When the fast flag clear-all bit, TFFCA, is set, any access to the timer counter registers clears TOF. 12.5.
PAGE 134
Standard Timer Module 12.5.14 Pulse Accumulator Control Register Address: $00A0 Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 = Unimplemented Figure 12-21. Pulse Accumulator Control Register (PACTL) Read: Anytime Write: Anytime PAEN — Pulse Accumulator Enable Bit PAEN enables the pulse accumulator.
PAGE 135
Registers and Reset Initialization CLK1 and CLK0 — Clock Select Bits CLK1 and CLK0 select the timer counter input clock as shown in Table 12-4. Table 12-4. Clock Selection CLK[1:0] Timer Counter Clock(1) 00 Timer prescaler clock(2) 01 PACLK 10 PACLK ------------------256 11 PACLK ------------------65,536 1. Changing the CLKx bits causes an immediate change in the timer counter clock input. 2. When PAE = 0, the timer prescaler clock is always the timer counter clock.
PAGE 136
Standard Timer Module PAIF — Pulse Accumulator Input Flag PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. Clear PAIF by writing to the pulse accumulator flag register with PAIF set.
PAGE 137
External Pins 12.5.17 Timer Test Register Address: $00AD Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 TCBYP PCBYP 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 12-24. Timer Test Register (TIMTST) Read: Anytime Write: Only in special mode (SMODN = 0) TCBYP — Timer Divider Chain Bypass Bit TCBYP divides the 16-bit free-running timer counter into two 8-bit halves. The clock drives both halves directly and bypasses the timer prescaler.
PAGE 138
Standard Timer Module 12.6.2 Pulse Accumulator Pin Setting the PAE bit in the pulse accumulator control register enables the pulse accumulator input pin, PAI. NOTE The PAI input and timer channel 7 use the same pin. To use the PAI input, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7. Also clear the channel 7 output compare mask bit, OC7M7. 12.7 Background Debug Mode If the TSBCK bit is clear, background debug mode has no effect on the timer.
PAGE 139
Interrupt Sources 12.9 Interrupt Sources Table 12-5.
PAGE 140
Standard Timer Module NOTE Due to input synchronizer circuitry, the minimum pulse width for a pulse accumulator input or an input capture input should always be greater than the width of two module clocks. Table 12-6. TIMPORT I/O Function In Out Data Direction Register Output Compare Action Reading at Data Bus Reading at Pin 0 0 Pin Pin 0 1 Pin Output compare action 1 1 Port data register Output compare action 1 0 Port data register Port data register 12.10.
PAGE 141
Using the Output Compare Function to Generate a Square Wave 12.11 Using the Output Compare Function to Generate a Square Wave This timer exercise is intended to utilize the output compare function to generate a square wave of predetermined duty cycle and frequency. Square wave frequency 1000 Hz, duty cycle 50% The program generates a square wave, 50 percent duty cycle, on output compare 2 (OC2). The signal will be measured by the M68HC11 on the UDLP1 board. It assumes a 8.
PAGE 142
Standard Timer Module ---------------------------------------------------------------------; MAIN PROGRAM ; ---------------------------------------------------------------------ORG $7000 ; 16K On-Board RAM, User code data area, ; ; start main program at $7000 MAIN: BSR TIMERINIT ; Subroutine used to initialize the timer: ; ; Output compare channel, no interrupts BSR SQWAVE ; Subroutine to generate square wave DONE: BRA DONE ; Branch to itself, Convinient for Breakpoint ;* ----------------------------------
PAGE 143
Chapter 13 Multiple Serial Interface (MSI) 13.1 Introduction The multiple serial interface (MSI) module consists of three independent serial I/O interfaces: • Two serial communication interfaces, SCI0 and SCI1 • One serial peripheral interface, SPI0 NOTE Port S shares its pins with the multiple serial interface (MSI). See 13.6 General-Purpose I/O Ports. 13.
PAGE 144
Multiple Serial Interface (MSI) 13.
PAGE 145
MSI Register Map 13.5 MSI Register Map Addr. Register Name $00C0 SCI 0 Baud Rate Register High (SC0BDH) See page 168. SCI 0 Baud Rate Register $00C1 Low (SC0BDL) See page 168. $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 $00C8 SCI 0 Control Register 1 (SC0CR1) See page 169. SCI 0 Control Register 2 (SC0CR2) See page 171. SCI 0 Status Register 1 (SC0SR1) See page 172. SCI 0 Status Register 2 (SC0SR2) See page 173. SCI 0 Data Register High (SC0DRH) See page 174.
PAGE 146
Multiple Serial Interface (MSI) Addr. $00CC $00CD $00CE $00CF $00D0 $00D1 Register Name SCI 1 Status Register 1 (SC1SR1) See page 172. SCI 1 Status Register 2 (SC1SR2) See page 173. SCI 1 Data Register High (SC1DRH) See page 174. SCI 1 Data Register Low (SC1DRL) See page 174. SPI 0 Control Register 1 (SP0CR1) See page 186. SPI 0 Control Register 2 (SP0CR2) See page 187. SPI 0 Baud Rate Register $00D2 (SP0BR) See page 188. $00D3 $00D5 $00D6 $00D7 SPI 0 Status Register (SP0SR) See page 189.
PAGE 147
General-Purpose I/O Ports 13.6 General-Purpose I/O Ports Port S shares its pins with the multiple serial interface (MSI). In all modes, port S pins PS7–PS0 are available for either general-purpose I/O or for SCI and SPI functions. 13.6.1 Port S Data Register Address: Read: Write: $00D6 Bit 7 6 5 4 3 2 1 Bit 0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 RXD1 TXD0 RXD0 Reset: Pin function: Unaffected by reset SS SCK MOSI MISO TXD1 Figure 13-3.
PAGE 148
Multiple Serial Interface (MSI) 13.6.2 Port S Data Direction Register Address: $00D7 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 Figure 13-4. Port S Data Direction Register (DDRS) Read: Anytime Write: Anytime DDRS7–DDRS0 — Port S Data Direction Bits These bits control the data direction of each port S pin. Setting a DDRS bit makes the pin an output; clearing a DDRS bit makes the pin an input.
PAGE 149
General-Purpose I/O Ports RDS — Reduced Drive Port S Bit Setting RDS lowers the drive capability of all port S output pins for lower power consumption and less noise. 1 = Reduced drive 0 = Full drive Table 13-1.
PAGE 150
Multiple Serial Interface (MSI) MC68HC812A4 Data Sheet, Rev.
PAGE 151
Chapter 14 Serial Communications Interface Module (SCI) 14.1 Introduction The serial communications interface (SCI) allows asynchronous serial communications with peripheral devices and other MCUs. 14.
PAGE 152
Serial Communications Interface Module (SCI) 14.
PAGE 153
Register Map 14.4 Register Map NOTE The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Addr. Register Name SCI 0 Baud Rate Register $00C0 High (SC0BDH) See page 168. SCI 0 Baud Rate Register $00C1 Low (SC0BDL) See page 168. $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 SCI 0 Control Register 1 (SC0CR1) See page 169.
PAGE 154
Serial Communications Interface Module (SCI) Addr. Register Name SCI 1 Baud Rate Register $00C9 Low (SC1BDL) See page 168. $00CA $00CB $00CC $00CD $00CE $00CF SCI 1 Control Register 1 (SC1CR1) See page 169. SCI 1 Control Register 2 (SC1CR2) See page 171. SCI 1 Status Register 1 (SC1SR1) See page 172. SCI 1 Status Register 2 (SC1SR2) See page 173. SCI 1 Data Register High (SC1DRH) See page 174. SCI 1 Data Register Low (SC1DRL) See page 174.
PAGE 155
Functional Description 14.5 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. 14.5.1 Data Format The SCI uses the standard NRZ mark/space data format illustrated in Figure 14-3.
PAGE 156
Serial Communications Interface Module (SCI) 14.5.2 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12–SBR0 bits determines the module clock divisor. The SBR bits are in the SCI baud rate registers (SCBDH and SCBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter.
PAGE 157
Functional Description INTERNAL BUS MODULE CLOCK ³ 16 BAUD DIVIDER SCI DATA REGISTERS H 11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0 L TXD PARITY GENERATION LOOP CONTROL BREAK (ALL 0s) PT SHIFT ENABLE PE LOAD FROM SCIDR T8 PREAMBLE (ALL 1s) MSB M START STOP SBR12–SBR0 TO RECEIVER LOOPS RSRC TRANSMITTER CONTROL SCI INTERRUPT REQUEST TDRE TE SBK TIE SCI INTERRUPT REQUEST TC TCIE Figure 14-4. SCI Transmitter Block Diagram To initiate an SCI transmission: 1.
PAGE 158
Serial Communications Interface Module (SCI) register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCCR2) is also set, the TDRE flag generates an SCI interrupt request. When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCCR2), the transmitter and receiver relinquish control of the port I/O pins.
PAGE 159
Functional Description NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out to the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character when the TDRE flag becomes set and immediately before writing the next byte to the SCI data register. 14.5.4 Receiver A block diagram of the SCI receiver is shown in Figure 14-5.
PAGE 160
Serial Communications Interface Module (SCI) 14.5.4.2 Character Reception During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register.
PAGE 161
Functional Description If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-5 summarizes the results of the data bit samples. Table 14-5.
PAGE 162
Serial Communications Interface Module (SCI) START BIT LSB 0 0 0 0 0 0 0 RT10 RT1 1 RT9 RT1 1 RT8 RT1 1 RT7 0 RT1 1 RT1 1 RT5 1 RT1 RXD SAMPLES RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT6 RT5 RT4 RT3 RT2 RT4 RT3 RT CLOCK COUNT RT2 RT CLOCK RESET RT CLOCK Figure 14-7. Start Bit Search Example 1 In Figure 14-8 noise is perceived as the beginning of a start bit although the verification sample at RT3 is high. The RT3 sample sets the noise flag.
PAGE 163
Functional Description Figure 14-10 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. PERCEIVED AND ACTUAL START BIT LSB 1 1 1 0 RT1 RT1 1 RT1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 SAMPLES RT1 RXD 1 0 RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT CLOCK COUNT RT2 RT CLOCK RESET RT CLOCK Figure 14-10.
PAGE 164
Serial Communications Interface Module (SCI) 14.5.4.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCSR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. 14.5.4.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate.
PAGE 165
Functional Description Fast Data Tolerance Figure 14-14 shows how much a fast received frame can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. STOP IDLE OR NEXT FRAME RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK DATA SAMPLES Figure 14-14.
PAGE 166
Serial Communications Interface Module (SCI) • the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters.
PAGE 167
Functional Description Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCCR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the receiver input to the output of the TXD pin driver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). The wired-OR mode select bit, WOMS, configures the TXD pin for full CMOS drive or for open-drain drive.
PAGE 168
Serial Communications Interface Module (SCI) 14.6 Register Descriptions and Reset Initialization This section provides register descriptions and reset initialization. 14.6.1 SCI Baud Rate Registers SCI0: $00C0 SCI1: $00C8 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 0 0 0 0 0 0 0 0 Figure 14-17.
PAGE 169
Register Descriptions and Reset Initialization 14.6.2 SCI Control Register 1 SCI0: $00C2 SCI1: $00CA Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 LOOPS WOMS RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 Reset: Figure 14-19. SCI Control Register 1 (SC0CR1 or SC1CR1) Read: Anytime Write: Anytime LOOPS — Loop Select Bit LOOPS enables loop operation. In loop operation the RXD pin is disconnected from the SCI, and the transmitter output goes into the receiver input.
PAGE 170
Serial Communications Interface Module (SCI) Table 14-7. Loop Mode Functions (Continued) LOOPS RSRC DDRSx(1) WOMS 1 1 0 x Single-wire mode; transmitter output disconnected TXD is high-impedance receiver input 1 1 1 0 Single-wire mode; TXD pin connected to receiver input 1 1 1 1 Single wire mode; TXD pin connected to receiver input TXD is open-drain for receiving and transmitting Function of TXD Pin 1. DDRSx means the data direction bit of the TXD pin.
PAGE 171
Register Descriptions and Reset Initialization 14.6.3 SCI Control Register 2 SCI0: $00C3 SCI1: $00CB Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 14-20. SCI Control Register 2 (SC0CR2 or SC1CR2) Read: Anytime Write: Anytime TIE — Transmitter Interrupt Enable Bit TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.
PAGE 172
Serial Communications Interface Module (SCI) SBK — Send Break Bit Toggling SBK sends one break character (10 or 11 logic 0s). As long as SBK is set, the transmitter sends logic 0s. 1 = Transmit break characters 0 = No break characters 14.6.4 SCI Status Register 1 SCI0: $00C4 SCI1: $00CC Read: Bit 7 6 5 4 3 2 1 Bit 0 TDRE TC RDRF IDLE OR NF FE PF 1 0 0 0 0 0 0 Write: Reset: 1 = Unimplemented Figure 14-21.
PAGE 173
Register Descriptions and Reset Initialization OR — Overrun Flag OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 with OR set and then reading the low byte of the SCI data register. 1 = Overrun 0 = No overrun NF — Noise Flag NF is set when the SCI detects noise on the receiver input.
PAGE 174
Serial Communications Interface Module (SCI) 14.6.6 SCI Data Registers SCI0: $00C6 SCI1: $00CE Bit 7 Read: 6 R8 T8 Write: 5 4 3 2 1 Bit 0 0 0 0 0 0 0 Reset: Unaffected by reset = Unimplemented Figure 14-23. SCI Data Register High (SC0DRH or SC1DRH) SCI0: $00C7 SCI1: $00CF Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 14-24.
PAGE 175
External Pin Descriptions 14.7 External Pin Descriptions This section provides a description of TXD and RXD, the SCI’s two external pins. 14.7.1 TXD Pin TXD is the SCI transmitter pin. TXD is available for general-purpose I/O when it is not configured for transmitter operation. 14.7.2 RXD Pin RXD is the SCI receiver pin. RXD is available for general-purpose I/O when it is not configured for receiver operation. 14.8 Modes of Operation The SCI functions the same in normal, special, and emulation modes.
PAGE 176
Serial Communications Interface Module (SCI) 14.10 Interrupt Sources Table 14-8. SCI Interrupt Sources Interrupt Source Flag Transmit data register empty Transmission complete Receive data register full Local Enable CCR Mask TDRE TIE I bit TC TCIE I bit RIE I bit ILIE I bit RDRF Receiver overrun Vector Address SCI0 SCI1 $FFD6, $FFD7 $FFD4, $FFD5 OR Receiver idle IDLE 14.11 General-Purpose I/O Ports Port S shares its pins with the multiple serial interface (MSI).
PAGE 177
Serial Character Transmission Using the SCI 14.12.2 Code Listing NOTE A comment line is delimited by a semicolon. If there is no code before comment, a semicolon (;) must be placed in the first column to avoid assembly errors. INCLUDE 'EQUATES.
PAGE 178
Serial Communications Interface Module (SCI) MC68HC812A4 Data Sheet, Rev.
PAGE 179
Chapter 15 Serial Peripheral Interface (SPI) 15.1 Introduction The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communications with peripheral devices. 15.
PAGE 180
Serial Peripheral Interface (SPI) 15.3 Block Diagram SPR2 SPR1 MSTR SPI DATA REGISTER (WRITE) BAUD RATE SELECT SPR0 CPHA CLOCK LOGIC SHIFT REGISTER CPOL P-CLOCK CLOCK DIVIDER SPI DATA REGISTER (READ) PUPS RDS SWOM SHIFT CONTROL LOGIC SSOE LSBF SPE SPI CONTROL MSTR SPC0 PIN CONTROL LOGIC MODF PORT S DATA DIRECTION REGISTER WCOL SPIF SPIE INTERRUPT REQUEST PORT S DATA REGISTER 7 6 5 4 MISO OR SISO MOSI OR MOMI SCK SS Figure 15-1. SPI Block Diagram MC68HC812A4 Data Sheet, Rev.
PAGE 181
Register Map 15.4 Register Map NOTE The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Addr. Register Name SPI 0 Control Read: $00D0 Register 1 (SP0CR1) Write: See page 186. Reset: SPI 0 Control Read: $00D1 Register 2 (SP0CR2) Write: See page 187. Reset: $00D2 SPI Baud Rate Read: Register (SP0BR) Write: See page 188.
PAGE 182
Serial Peripheral Interface (SPI) 15.5 Functional Description The SPI allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. In master mode, the SPI generates the synchronizing clock and initiates transmissions. In slave mode, the SPI depends on a master peripheral to start and synchronize transmissions. 15.5.1 Master Mode The SPI operates in master mode when the master mode bit, MSTR, is set.
PAGE 183
Functional Description becomes set, the byte from the master transfers to the SPI data register. The byte remains in a read buffer until replaced by the next byte from the master. 15.5.3 Baud Rate Generation A clock divider in the SPI produces eight divided P-clock signals. The P-clock divisors are 2, 4, 8, 16, 32, 64, 128, and 256. The SPR[2:1:0] bits select one of the divided P-clock signals to control the rate of the shift register.
PAGE 184
Serial Peripheral Interface (SPI) MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTER SS SLAVE SS CPHA = 0 Figure 15-5. Slave SS Toggling When CPHA = 0 When CPHA = 1, the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SS pin can remain low between transmissions. This format may be preferable in systems having only one slave driving the master MISO line. NOTE The slave SCK pin must be in the proper idle state before the slave is enabled.
PAGE 185
Functional Description 15.5.5 SS Output In master mode only, the SS pin can function as a chip-select output for connection to the SS input of a slave. The master SS output automatically selects the slave by going low for each transmission and deselects the slave by going high during each idling state. Enable the SS output by setting the master mode bit, MSTR, the slave-select output enable bit, SSOE, and the data direction bit of the SS pin. MSTR and SSOE are in SPI control register 1. Table 15-1.
PAGE 186
Serial Peripheral Interface (SPI) 15.6 SPI Register Descriptions and Reset Initialization This section describes the SPI registers and reset initialization. 15.6.1 SPI Control Register 1 Address: $00D0 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF 0 0 0 0 0 1 0 0 Figure 15-9. SPI Control Register 1 (SP0CR1) Read: Anytime Write: Anytime SPIE — SPI Interrupt Enable Bit SPIE enables the SPIF and MODF flags to generate interrupt requests.
PAGE 187
SPI Register Descriptions and Reset Initialization SSOE — Slave Select Output Enable Bit SSOE enables the output function of master SS pin when the DDRS7 bit is also set. 1 = SS output enabled 0 = SS output disabled LSBF — LSB First Bit LSBF enables least-significant-bit-first transmissions. It does not affect the position of data in the SPI data register; reads and writes of the SPI data register always have the MSB in bit 7.
PAGE 188
Serial Peripheral Interface (SPI) 15.6.3 SPI Baud Rate Register Address: $00D2 Read: Bit 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 Write: Reset: 2 1 Bit 0 SPR2 SPR1 SPR0 0 0 0 = Unimplemented Figure 15-11. SPI Baud Rate Register (SP0BR) Read: Anytime Write: Anytime SPR2–SPR0 — SPI Clock Rate Select Bits These bits select one of eight SPI baud rates as shown in Table 15-3. Reset clears SPR2–SPR0, selecting E-clock divided by two. Table 15-3.
PAGE 189
SPI Register Descriptions and Reset Initialization 15.6.4 SPI Status Register Address: $00D3 Read: Bit 7 6 5 4 3 2 1 Bit 0 SPIF WCOL 0 MODF 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 15-12. SPI Status Register (SP0SR) Read: Anytime Write: Has no meaning or effect SPIF — SPI Flag SPIF is set after the eighth serial clock cycle of a transmissson. SPIF generates an interrupt request if the SPIE bit in SPI control register 1 is set also.
PAGE 190
Serial Peripheral Interface (SPI) 15.6.5 SPI Data Register Address: $00D5 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Reset: Unaffected by reset Figure 15-13. SPI Data Register (SP0DR) Read: Anytime; normally, only after SPIF flag set Write: Anytime a data transfer is not taking place The SPI data register is both the input and output register for SPI data. Reads are double-buffered but writes cause data to be written directly into the SPI shift register.
PAGE 191
Low-Power Options 15.7.4 SS (Slave Select) The SS pin has multiple functions that depend on SPI configuration: • The SS pin of a slave SPI is always configured as an input and allows the slave to be selected for transmission. • When the CPHA bit is clear, the SS pin signals the start of a transmission. • The SS pin of a master SPI can be configured as a mode-fault input, a slave-select output, or a general-purpose output.
PAGE 192
Serial Peripheral Interface (SPI) 15.9 Interrupt Sources Table 15-4. SPI Interrupt Sources Interrupt Source Transmission complete Mode fault Flag SPIF MODF Local Enable CCR Mask Vector Address SPIE I bit $FFD8, $FFD9 15.10 General-Purpose I/O Ports Port S shares its pins with the multiple serial interface (MSI). In all modes, port S pins PS7–PS0 are available for either general-purpose I/O or for SCI and SPI functions. See Chapter 13 Multiple Serial Interface (MSI). 15.
PAGE 193
Synchronous Character Transmission Using the SPI ; ---------------------------------------------------------------------;* SUBROUTINE INIT: ; ---------------------------------------------------------------------INIT: BSET PORTS,#$80 ; SET SS Line High to prevent glitch MOVB #$E0,DDRS ; Configure PORT S input/ouput levels ; MOSI, SCK, SS* = ouput, MISO=Input MOVB #$07,SP0BR ; Select serial clock baud rate < 100 KHz MOVB #$12,SP0CR1 ; Configure SPI(SP0CR1): No SPI interrupts, ; MSTR=1, CPOL=0, CPHA=0
PAGE 194
Serial Peripheral Interface (SPI) MC68HC812A4 Data Sheet, Rev.
PAGE 195
Chapter 16 Analog-to-Digital Converter (ATD) 16.1 Introduction The analog-to-digital converter (ATD) is an 8-channel, 8-bit, multiplexed-input, successive approximation analog-to-digital converter, accurate to ±1 least significant bit (LSB). It does not require external sample and hold circuits because of the type of charge redistribution technique used. The ATD converter timing can be synchronized to the system P-clock.
PAGE 196
Analog-to-Digital Converter (ATD) 16.3 Block Diagram VRH VRL RC DAC ARRAY AND COMPARATOR VDDA VSSA SAR CHANNEL 0 MODE AND TIMING CONTROL CHANNEL 1 ANALOG MUX AND SAMPLE BUFFER AMP CHANNEL 2 AN7/PAD7 AN6/PAD6 AN5/PAD5 AN4/PAD4 AN3/PAD3 AN2/PAD2 AN1/PAD1 AN0/PAD0 PORT AD DATA INPUT REGISTER CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CLOCK SELECT/PRESCALE Figure 16-1. ATD Block Diagram MC68HC812A4 Data Sheet, Rev.
PAGE 197
Register Map 16.4 Register Map NOTE The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Addr. $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 $0068 $0069 Register Name ATD Control Register 0 (ATDCTL0) See page 199. ATD Control Register 1 (ATDCTL1) See page 199. ATD Control Register 2 (ATDCTL2) See page 200.
PAGE 198
Analog-to-Digital Converter (ATD) Addr. $006F $0070 $0072 $0074 $0076 $0078 $007A $007C $007E Register Name Port AD Data Input Register (PORTAD) See page 207. ATD Result Register 0 (ADR0H) See page 206. ATD Result Register 1 (ADR1H) See page 206. ATD Result Register 2 (ADR2H) See page 206. ATD Result Register 3 (ADR3H) See page 206. ATD Result Register 4 (ADR4H) See page 206. ATD Result Register 5 (ADR5H) See page 206. ATD Result Register 6 (ADR6H) See page 206.
PAGE 199
Registers and Reset Initialization In both modes, the CCF flag associated with each register is set when that register is loaded with the appropriate conversion result. That flag is cleared automatically when that result register is read. The conversions are started by writing to the control registers. The ATD control register 4 selects the clock source and sets up the prescaler. Writes to the ATD control registers initiate a new conversion sequence.
PAGE 200
Analog-to-Digital Converter (ATD) 16.6.3 ATD Control Register 2 Address: $0062 Read: Write: Reset: Bit 7 6 5 ADPU AFFC AWAI 0 0 0 4 3 2 0 0 0 0 0 0 1 ASCIE 0 Bit 0 ASCIF 0 = Unimplemented Figure 16-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime except ASCIF flag, which is read-only NOTE Writing to this register aborts the current conversion sequence. ADPU — ATD Power-up Bit ADPU enables the clock signal to the ATD and powers up its analog circuits.
PAGE 201
Registers and Reset Initialization 16.6.4 ADT Control Register 3 Address: $0063 Read: Bit 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: 1 Bit 0 FRZ1 FRZ0 0 0 = Unimplemented Figure 16-6. ATD Control Register 3 (ATDCTL3) FRZ1 and FRZ0 — Freeze Bits The FRZ bits suspend ATD operation for background debugging. When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint is encountered.
PAGE 202
Analog-to-Digital Converter (ATD) PRS[4:0] — Prescaler Select Bits The prescaler divides the P-clock by the binary value written to PRS[4:0] plus one. To assure symmetry of the prescaler output, an additional divide-by-two circuit generates the ATD module clock. Clearing PRS[4:0] means the P-clock is divided only by the divide-by-two circuit. The reset state of PRS[4:0] is 00001, giving a total P-clock divisor of four, which is appropriate for nominal operation at 2 MHz.
PAGE 203
Registers and Reset Initialization MULT — Multichannel Conversion Bit Refer to Table 16-4. 1 = Conversions of sequential channels 0 = Conversions of a single input channel selected by the CD, CC, CB, and CA bits CD, CC, CB, and CA — Channel Select Bits The channel select bits select the input to convert. LT = 1, the ATD sequencer selects Table 16-4.
PAGE 204
Analog-to-Digital Converter (ATD) 16.6.7 ATD Status Registers Address: $0066 Read: Bit 7 6 5 4 3 2 1 Bit 0 SCF 0 0 0 0 CC2 CC1 CC0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 16-9. ATD Status Register 1 (ATDSTAT1) Address: $0067 Read: Bit 7 6 5 4 3 2 1 Bit 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 16-10.
PAGE 205
Registers and Reset Initialization 16.6.8 ATD Test Registers Address: $0068 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 0 0 0 0 0 0 0 0 Figure 16-11. ATD Test Register 1 (ATDTEST1) Address: $0069 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0 0 0 0 0 0 0 0 0 Figure 16-12.
PAGE 206
Analog-to-Digital Converter (ATD) 16.6.9 ATD Result Registers Address: Read: ADR0H: ADR1H: ADR2H: ADR3H: ADR4H: ADR5H: ADR6H: ADR7H: $0070 $0072 $0074 $0076 $0078 $007A $007C $007E Bit 7 6 5 4 3 2 1 Bit 0 ADRxH7 ADRxH6 ADRxH5 ADRxH4 ADRxH3 ADRxH2 ADRxH1 ADRxH0 Write: Reset: Indeterminate = Unimplemented Figure 16-13.
PAGE 207
Interrupt Sources 16.7.3 Stop Mode The ATD is inactive in stop mode for reduced power consumption. The STOP instruction aborts any conversion sequence in progress. 16.8 Interrupt Sources Table 16-5. ATD Interrupt Sources Interrupt Source Conversion sequence complete Flag Local Enable CCR Mask Vector Address ASCIF ASCIE I bit $FFD2, $FFD3 NOTE The ASCIF flag is set only when a conversion sequence is completed and ASCIE = 1 or interrupts on the analog-to-digital converter (ATD) module are enabled.
PAGE 208
Analog-to-Digital Converter (ATD) 16.11 Using the ATD to Measure a Potentiometer Signal This exercise allows the student to utilize the ATD on the HC12 to measure a potentiometer signal output routed from the UDLP1 board to the HC12 ATD pin PAD6. First the ATDCTL registers are initialized. A delay loop of 100 µs is then executed. The resolution is set up followed by a conversion set up on channel 6. After waiting for the status bit to set, the result goes to the D accumulator.
PAGE 209
Using the ATD to Measure a Potentiometer Signal ; ; ; ; ; ; ; ; ---------------------------------------------Subroutine CONVERT: ; ---------------------------------------------Set-up ATD, make single conversion and store the result to a memory location.
PAGE 210
Analog-to-Digital Converter (ATD) MC68HC812A4 Data Sheet, Rev.
PAGE 211
Chapter 17 Development Support 17.1 Introduction This section describes: • Instruction queue • Queue tracking signals • Background debug mode (BDM) • Instruction tagging 17.2 Instruction Queue The CPU12 instruction queue provides at least three bytes of program information to the CPU when instruction execution begins. The CPU12 always completely finishes executing an instruction before beginning to execute the next instruction.
PAGE 212
Development Support Program information is fetched a few cycles before it is used by the CPU. To monitor cycle-by-cycle CPU activity, it is necessary to externally reconstruct what is happening in the instruction queue. Internally, the MCU only needs to buffer the data from program fetches. For system debug, it is necessary to keep the data and its associated address in the reconstructed instruction queue.
PAGE 213
Background Debug Mode (BDM) Figure 17-1 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target M68HC12 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target E cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges.
PAGE 214
Development Support E-CLOCK TARGET MCU HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU SPEED-UP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure 17-2.
PAGE 215
Background Debug Mode (BDM) BDM becomes active at the next instruction boundary following execution of the BDM BACKGROUND command, but tags activate BDM before a tagged instruction is executed. In special single-chip mode, background operation is enabled and active immediately out of reset. This active case replaces the M68HC11 boot function and allows programming a system with blank memory. While BDM is active, a set of BDM control registers are mapped to addresses $FF00 to $FF06.
PAGE 216
Development Support Table 17-2.
PAGE 217
BDM Registers 17.4 BDM Registers Seven BDM registers are mapped into the standard 64-Kbyte address space when BDM is active. The registers can be accessed with the hardware READ_BD and WRITE_BD commands, but must not be written during BDM operation. Most users are only interested in the STATUS register at $FF01; other registers are for use only by BDM firmware and logic.
PAGE 218
Development Support 17.4.1.2 Firmware Command Address: $FF00 Read: Write: Reset: Bit 7 6 5 H/F DATA R/W 0 0 0 4 3 2 TTAGO 0 1 Bit 0 REGN 0 0 0 0 Figure 17-5. BDM Instruction Register (INSTRUCTION) The bits in the BDM instruction register have the following meanings when a firmware command is executed.
PAGE 219
BDM Registers 17.4.2 BDM Status Register Address: $FF01 Bit 7 6 5 4 3 2 1 Bit 0 ENBDM EDMACT ENTAG SDV TRACE 0 0 0 Reset: 0 0 0 0 0 0 0 0 Single-chip peripheral: 1 0 0 0 0 0 0 0 Read: Write: Figure 17-6. BDM Status Register (STATUS) This register can be read or written by BDM commands or firmware. ENBDM — Enable BDM Bit (permit active background debug mode) 1 = BDM can be made active to allow firmware commands.
PAGE 220
Development Support 17.4.4 BDM Address Register Address: $FF04 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 A15 A14 A13 A12 A11 A10 A9 A8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 Address: $FF05 Read: Write: Reset: Figure 17-8. BDM Address Register (ADDRESS) This 16-bit register is temporary storage for BDM hardware and firmware commands. 17.4.
PAGE 221
Chapter 18 Electrical Characteristics 18.1 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 18.4 DC Electrical Characteristics for guaranteed operating conditions. Rating Symbol Value Unit VDD VDDA VDDX –0.3 to +6.5 V Input voltage VIn –0.3 to +6.
PAGE 222
Electrical Characteristics 18.2 Functional Operating Range Rating Operating temperature range(1) MC68HC812A4PV8 MC68HC812A4CPV8 Operating voltage range Symbol Value Unit TA TL to TH 0 to +70 −40 to +85 °C VDD 5.0 ± 10% V 1. For additional information, refer to the technical supplement document for 3.3 volt specifications (MC68C812A4) . This supplement can be found at http://freescale.com 18.
PAGE 223
DC Electrical Characteristics 18.4 DC Electrical Characteristics Characteristic(1) Symbol Min Max Unit Input high voltage, all inputs VIH 0.7 × VDD VDD + 0.3 V Input low voltage, all inputs VIL VSS−0.3 0.2 × VDD V VOH VDD − 0.2 VDD − 0.8 — — V VDD − 0.2 VDD − 0.8 — — — — VSS +0.2 VSS +0.4 — — VSS +0.2 VSS +0.4 — — — ±1 ±10 ±10 — ±2.5 — — — 10 15 20 Output high voltage, all I/O and output pins Normal drive strength IOH = −10.0 µA IOH = −0.8 mA Reduced drive strength IOH = −4.
PAGE 224
Electrical Characteristics 18.5 Supply Current Characteristic(1) Symbol Maximum total supply current Run Single-chip mode Expanded mode Wait, all peripheral functions shut down Single-chip mode Expanded mode Stop, single-chip mode, no clocks –40 °C to +85 °C +85 °C to +105 °C +105 °C to +125 °C 8 MHz Typical 2 MHz 4 MHz 8 MHz Unit 30 47 15 25 25 40 40 65 mA mA 7 8 1.
PAGE 225
ATD DC Electrical Characteristcs 18.7 ATD DC Electrical Characteristcs Characteristic(1) Symbol Min Max Unit Analog supply voltage VDDA 4.5 5.5 V Analog supply current, normal operation IDDA — 1.0 mA Reference voltage, low VRL VSSA VDDA/2 V Reference voltage, high VRH VDDA/2 VDDA V VRH−VRL 4.5 5.
PAGE 226
Electrical Characteristics 18.9 ATD AC Operating Characteristics Characteristic(1) Symbol Min Max Unit ATD operating clock frequency fATDCLK 0.5 2.0 MHz Conversion time per channel 0.5 MHz ≤ fATDCLK ≤ 2 MHz 18 ATD clocks 32 ATD clocks tCONV 8.0 15.0 32.0 60.0 — 50 Stop recovery time VDDA = 5.0 V tSR µs µs 1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, ATD clock = 2 MHz, unless otherwise noted 18.
PAGE 227
Control Timing 18.11 Control Timing 8.0 MHz Characteristic Symbol Unit Min Max fo dc 8.0 MHz tcyc 125 — ns fXTAL — 16.0 MHz External oscillator frequency 2 fo dc 16.
PAGE 228
Electrical Characteristics 228 VDD EXTAL MC68HC812A4 Data Sheet, Rev. 7 4098 tcyc ECLK tPCSU PWRSTL RESET tMPH tMPS MODA, MODB INTERNAL ADDRESS FFFE FFFE FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC FFFE FFFE FFFE Note: Reset timing is subject to change. Figure 18-2.
PAGE 229
Freescale Semiconductor INTERNAL CLOCKS IRQ1 PWIRQ MC68HC812A4 Data Sheet, Rev. 7 IRQ or XIRQ tSTOPDELAY(3) ECLK ADDRESS4 SP-6 SP-8 SP-9 FREE FREE OPT FETCH 1ST EXEC Resume program with instruction which follows the STOP instruction. ADDRESS5 SP-6 SP-8 SP-9 FREE VECTOR FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC Notes: 1. Edge-sensitive IRQ pin (IRQE bit = 1) 2. Level-sensitive IRQ pin (IRQE bit = 0) 3. tSTOPDELAY = 4098 tcyc if DLY bit = 1 or 2 tcyc if DLY = 0. 4.
PAGE 230
tPCSU IRQ, XIRQ, OR INTERNAL INTERRUPTS tWRS SP – 2 ADDRESS SP – 4 SP – 9 SP – 6 . . . SP – 9 SP – 9. . . SP – 9 FREE SP – 9 VECTOR ADDRESS PC, IY, IX, B:A, , CCR STACK REGISTERS R/W Note: RESET also causes recovery from WAIT. MC68HC812A4 Data Sheet, Rev. 7 Figure 18-4.
PAGE 231
Peripheral Port Timing 18.12 Peripheral Port Timing 8.0 MHz Characteristic Symbol Unit Min Max fo dc 8.0 MHz tcyc 125 — ns Peripheral data setup time, MCU read of ports tPDSU = tcyc/2 + 30 tPDSU 102 — ns Peripheral data hold time, MCU read of ports tPDH 0 — ns Delay time, peripheral data write, MCU write to ports tPWD — 40 ns Frequency of operation (E-clock frequency) E-clock period MCU READ OF PORT ECLK tPDSU tPDH PORTS Figure 18-6.
PAGE 232
Electrical Characteristics 18.13 Non-Multiplexed Expansion Bus Timing Characteristic(1), (2) Num Frequency of operation (E-clock frequency) 8 MHz Delay — Symbol Unit Min Max fo dc 8.
PAGE 233
Non-Multiplexed Expansion Bus Timing 1 2 3 ECLK 22 7 6 5 ADDR[15:0] 23 11 12 DATA[15:0] READ 13 15 14 DATA[15:0] WRITE 16 17 18 19 20 21 R/W LSTRB (W/O TAG ENABLED) 29 26 27 28 CS Note: Measurement points shown are 20% and 70% of VDD. Figure 18-8. Non-Multiplexed Expansion Bus Timing Diagram MC68HC812A4 Data Sheet, Rev.
PAGE 234
Electrical Characteristics 18.
PAGE 235
SPI Timing SS(1) OUTPUT 5 2 1 SCK CPOL = 0 (OUTPUT 3 12 4 4 13 SCK CPOL = 1 OUTPUT 6 7 MISO INPUT MSB IN(2) BIT 6 . . . 1 10 LSB IN 10 MOSI OUTPUT MSB OUT(2) 11 BIT 6 . . . 1 LSB OUT Notes: 1. SS output mode (DDS7 = 1, SSOE = 1) 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB A) SPI Master Timing (CPHA = 0) SS(1) OUTPUT 5 1 2 13 12 12 13 3 SCK CPOL = 0 OUTPUT 4 4 SCK CPOL = 1 OUTPUT 6 MISO INPUT 7 MSB IN(2) BIT 6 . . .
PAGE 236
Electrical Characteristics SS INPUT 5 1 13 12 12 13 3 SCK CPOL = 0 INPUT 4 2 4 SCK CPOL = 1 INPUT 9 8 MISO OUTPUT 10 6 MOSI INPUT BIT 6 . . . 1 MSB OUT SLAVE 11 11 SLAVE LSB OUT SEE NOTE 7 BIT 6 . . . 1 MSB IN LSB IN Note: Not defined but normally MSB of character just received A) SPI Slave Timing (CPHA = 0) SS INPUT 5 3 1 2 13 12 12 13 SCK CPOL = 0 INPUT 4 4 SCK CPOL = 1 INPUT SEE NOTE 8 MOSI INPUT SLAVE 6 9 11 10 MISO OUTPUT MSB OUT BIT 6 . . .
PAGE 237
Chapter 19 Mechanical Specifications 19.1 Introduction This section provides dimensions for the 112-lead low-profile quad flat pack (LQFP). 19.2 Package Dimensions Refer to the following pages for detailed package dimensions. MC68HC812A4 Data Sheet, Rev.
PAGE 238
PAGE 239
PAGE 240
PAGE 241
PAGE 242
How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.