Datasheet

Clock Module
MC68HC812A4 Data Sheet, Rev. 7
102 Freescale Semiconductor
Figure 10-2 shows clock timing relationships. Four bits in the CLKCTL register control the base clock and
M-clock divide selection (÷1, ÷2, ÷4, and ÷8 are selectable).
Figure 10-2. Internal Clock Relationships
10.3 Register Map
NOTE
The register block can be mapped to any 2-Kbyte boundary within the
standard 64-Kbyte address space. The register block occupies the first 512
bytes of the 2-Kbyte block. This register map shows default addressing
after reset.
Addr.Register Name Bit 7654321Bit 0
$0014
Real-Time Interrupt
Control Reg. (RTICTL)
See page 105.
Read:
RTIE RSWAI RSBCK
0
RTBYP RTR2 RTR1 RTR0
Write:
Reset:00000000
$0015
Real-Time Interrupt Flag
Register (RTIFLG)
See page 107.
Read:
RTIF
0000000
Write:
Reset:00000000
$0016
COP Control Register
(COPCTL)
See page 107.
Read:
CME FCME FCM FCOP DISR CR2 CR1 CR0
Write:
Reset:00000000
$0017
Arm/Reset COP Register
(COPRST)
See page 109.
Read: 0 0 0 00000
Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset:00000000
= Unimplemented
Figure 10-3. Clock Function Register Map
T1CLK
T2CLK
T3CLK
T4CLK
INTERNAL ECLK
PCLK
MCLK
Note: The MCLK depends on the chosen divider settings in the CLKCTL register.
8
MCLK
4
MCLK
2
MCLK
1