Datasheet

Registers and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 105
Figure 10-6. Clock Chain for SPI, ATD, and BDM
10.5 Registers and Reset Initialization
This section describes the registers and reset initialization.
10.5.1 Real-Time Interrupt Control Register
Read: Anytime
Write: Varies from bit to bit
Address: $0014
Bit 7654321Bit 0
Read:
RTIE RSWAI RSBCK
0
RTBYP RTR2 RTR1 RTR0
Write:
Reset:00000000
= Unimplemented
Figure 10-7. Real-Time Interrupt Control Register (RTICTL)
PCLK
BKGD OUT
BKGD
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
SPI BIT RATE
REGISTER: SP0BR
BITS:
SPR2:SPR1:SPR0
0:0:0
BDM BIT CLOCK
Receive: Detect falling edge; count 12 E-clocks; sample input
Transmit 1: Detect falling edge; count six E-clocks while output is
high impedance; drive out one E cycle pulse high; return output
to high impedance
Transmit 0: Detect falling edge; drive out low; count nine E-clocks;
drive out one E cycle pulse high; return output to high-impedance
PRS[4:0]
5-BIT ATD
PRESCALER
÷ 2
ATD CLOCK
BKGD PIN
LOGIC
SYNCHRONIZER
÷ 2
ECLK
DIRECTION
BKGD IN