Datasheet

Registers and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 107
10.5.2 Real-Time Interrupt Flag Register
RTIF — Real-Time Interrupt Flag
RTIF is set when the timeout period elapses. RTIF generates an interrupt request if the RTIE bit is set
in the RTI control register. Clear RTIF by writing to the real-time interrupt flag register with RTIF set.
1 = Timeout period elapsed
0 = Timeout period not elapsed
10.5.3 COP Control Register
Read: Anytime
Write: Varies from bit to bit
CME — Clock Monitor Enable Bit
Write: Anytime
CME enables the clock monitor. If the force clock monitor enable bit, FCME, is set, CME has no
meaning or effect.
1 = Clock monitor enabled
0 = Clock monitor disabled
NOTE
Clear the CME bit before executing a STOP instruction and set the CME bit
after exiting stop mode.
FCME — Force Clock Monitor Enable Bit
Write: Once in normal modes, anytime in special modes
FCME forces the clock monitor to be enabled until a reset occurs. When FCME is set, the CME bit has
no effect.
1 = Clock monitor enabled
0 = CME bit enables or disables clock monitor
NOTE
Clear the FCME bit in applications that use the STOP instruction and the
clock monitor.
Address: $0015
Bit 7654321Bit 0
Read:
RTIF
0000000
Write:
Reset:00000000
= Unimplemented
Figure 10-8. Real-Time Interrupt Flag Register (RTIFLG)
Address: $0016
Bit 7654321Bit 0
Read:
CME FCME FCM FCOP DISR CR2 CR1 CR0
Write:
Reset:00000000
Figure 10-9. COP Control Register (COPCTL)